Add 8 programs

src/0.asm

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+;delay_01.spn
+;POT0 = delay time
+;POT1 = feedback
+;POT2 =
+
+EQU	    length		    32767
+EQU	    smooth		    0.000125
+
+MEM	    echo		    length
+
+EQU     pot0Smooth	    REG0
+EQU     delayOut		REG1
+EQU     feedback		REG2
+EQU     dryInput		REG3
+
+;POT0 setup
+RDAX	POT0, 1
+RDFX	pot0Smooth, smooth
+WRAX	pot0Smooth, 0
+
+;POT0 delay scaling
+RDAX 	pot0Smooth, 1
+SOF	    0.96, 0.04 ;40ms to 1000ms
+WRAX 	ADDR_PTR, 0
+
+;Mix the dry input with the delay out
+RDAX    delayOut, 0.5
+MULX    POT1
+RDAX    ADCL, 0.5
+WRAX    dryInput, 1
+WRA     echo, 0
+
+;Delay output
+RMPA    1
+WRAX    delayOut, 0
+
+;Form output
+RDAX    delayOut, 1
+WRAX    DACL, 1
+WRAX    DACR, 0

src/1.asm

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+; FV-1 Testing Bank
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 1 : Output Max Val
+	clr			; clear ACC
+	or	0x0	; load max value to ACC
+	wrax	DACL,0.0	; Write to DACL

src/2.asm

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+; FV-1 Testing Bank
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 2 : Output Min Val
+	clr			; clear ACC
+	or	0x800000	; load min value to ACC
+	wrax	DACL,0.0	; Write to DACL

src/3.asm

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+; FV-1 Testing Bank
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 3 : Check WRAX/LDAX
+;
+; Expected output: max (pass) or min (fail)
+
+; Immediates
+equ	chkhi	0xaaaaaa	; test pattern one
+equ	chklo	0x555555	; test pattern two
+equ	maxval	0x7fffff	; maximum immediate value
+equ	minval	0x800000	; minimim immediate value
+
+; Registers
+equ	CHK	REG0		; register to hold check val
+
+test1:	clr
+	or	chkhi
+	wrax	CHK,1.0		; write immediate to register
+	or	0xffffff	; set all bits
+	ldax	CHK		; move check value into ACC
+	xor	chkhi		; compare with required value
+	skp	ZRO,test2	; if same, continue
+	clr
+	skp	ZRO,fail	; else skip to fail
+
+test2:	clr
+	or	chklo
+	wrax	CHK,1.0
+	or	0xffffff
+	ldax	CHK
+	xor	chklo
+	skp	ZRO,pass	; both tests ok
+
+fail:	clr
+	or	minval		; write fail flag
+	wrax	DACL,0.0	; output to DAC
+	skp	ZRO,end
+pass:	clr
+	or	maxval		; write pass flag
+	wrax	DACL,0.0	; output to DAC
+end:	nop

src/4.asm

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+; FV-1 Testing Bank
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 4 : Output Range
+;
+; Manually sweep output over all values
+;
+; Expected output: sawtooth with period 2**24/fs (~512s)
+
+; Waveform parameters
+equ	maxval	0x7fffff	; ACC maximum
+equ	minval	0x800000	; ACC minimum
+equ	incval	0x1		; per sample increment
+
+; Registers
+equ	PREV	REG0		; last output
+equ	CUR	REG1		; next output
+equ	MAX	REG3		; reg to store maxval
+equ	MIN	REG4		; reg ro store minval
+equ	INC	REG5		; reg to store incval
+
+; Prepare constants
+	skp	RUN,main
+	clr
+	or	maxval
+	wrax	MAX,0.0
+	or	minval
+	wrax	MIN,0.0
+	or	incval
+	wrax	INC,0.0
+
+main:	ldax	PREV		; read previous output
+	xor	maxval		; compare with maximum value
+	skp	ZRO,tomin	; if PREV was as max, change to MIN
+
+incr:	ldax	INC		; load increment into ACC
+	rdax	PREV,1.0	; load acc with PREV + INC
+	wrax	CUR,0.0		; store to CUR and clear ACC
+	skp	ZRO,output	; skip to output
+
+tomin:	ldax	MIN		; load minimum val into ACC
+	wrax	CUR,0.0		; store minimum in CUR and clear ACC
+	skp	ZRO,output	; skip to output
+
+output: ldax	CUR		; load the computed value into ACC
+	wrax	PREV,1.0	; store value in PREV register
+	wrax	DACL,0.0	; output value to DAC

src/5.asm

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+; FV-1 Testing Bank
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 5 : PACC Init Val
+;
+; Expected output: 0.0
+
+	skp	RUN,output
+	wrlx	REG0,0.0	; copy PACC into ACC
+	wrax	REG1,0.0
+output:	ldax	REG1
+	wrax	DACL,0.0	; output stored value

src/6.asm

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+; FV-1 Testing Bank A
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 6 : ACC Init Val
+;
+;	note: also copies ADCL into delay for use with program 7
+;
+; Expected output: 0.0
+
+mem	delay	1
+
+	skp	RUN,output
+	wrax	REG1,0.0	; store ACC init value
+output:	ldax	REG1
+	wrax	DACL,0.0
+	ldax	ADCL
+	wra	delay,1.0
+	wrax	DACR,0.0

src/7.asm

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+; FV-1 Testing Bank A
+;
+; Check behaviour of FV-1 against documentation
+;
+
+; Program 7 : Delay Init Val
+;
+; Expected output: 0.0
+
+mem	delay	1
+
+	clr
+	rda	delay,1.0	; read from empty delay
+	wrax	DACL,0.0