From e092efdac68859b699345abd536e1c3ee13ef999 Mon Sep 17 00:00:00 2001 From: heck Date: Wed, 9 Aug 2023 01:01:47 +0200 Subject: [PATCH] Add 8 programs --- src/0.asm | 40 ++++++++++++++++++++++++++++++++++++++++ src/1.asm | 9 +++++++++ src/2.asm | 9 +++++++++ src/3.asm | 44 ++++++++++++++++++++++++++++++++++++++++++++ src/4.asm | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ src/5.asm | 14 ++++++++++++++ src/6.asm | 20 ++++++++++++++++++++ src/7.asm | 14 ++++++++++++++ 8 files changed, 199 insertions(+) create mode 100644 src/0.asm create mode 100644 src/1.asm create mode 100644 src/2.asm create mode 100644 src/3.asm create mode 100644 src/4.asm create mode 100644 src/5.asm create mode 100644 src/6.asm create mode 100644 src/7.asm diff --git a/src/0.asm b/src/0.asm new file mode 100644 index 0000000..45c0f63 --- /dev/null +++ b/src/0.asm @@ -0,0 +1,40 @@ +;delay_01.spn +;POT0 = delay time +;POT1 = feedback +;POT2 = + +EQU length 32767 +EQU smooth 0.000125 + +MEM echo length + +EQU pot0Smooth REG0 +EQU delayOut REG1 +EQU feedback REG2 +EQU dryInput REG3 + +;POT0 setup +RDAX POT0, 1 +RDFX pot0Smooth, smooth +WRAX pot0Smooth, 0 + +;POT0 delay scaling +RDAX pot0Smooth, 1 +SOF 0.96, 0.04 ;40ms to 1000ms +WRAX ADDR_PTR, 0 + +;Mix the dry input with the delay out +RDAX delayOut, 0.5 +MULX POT1 +RDAX ADCL, 0.5 +WRAX dryInput, 1 +WRA echo, 0 + +;Delay output +RMPA 1 +WRAX delayOut, 0 + +;Form output +RDAX delayOut, 1 +WRAX DACL, 1 +WRAX DACR, 0 \ No newline at end of file diff --git a/src/1.asm b/src/1.asm new file mode 100644 index 0000000..fad1585 --- /dev/null +++ b/src/1.asm @@ -0,0 +1,9 @@ +; FV-1 Testing Bank +; +; Check behaviour of FV-1 against documentation +; + +; Program 1 : Output Max Val + clr ; clear ACC + or 0x0 ; load max value to ACC + wrax DACL,0.0 ; Write to DACL diff --git a/src/2.asm b/src/2.asm new file mode 100644 index 0000000..5d63f48 --- /dev/null +++ b/src/2.asm @@ -0,0 +1,9 @@ +; FV-1 Testing Bank +; +; Check behaviour of FV-1 against documentation +; + +; Program 2 : Output Min Val + clr ; clear ACC + or 0x800000 ; load min value to ACC + wrax DACL,0.0 ; Write to DACL diff --git a/src/3.asm b/src/3.asm new file mode 100644 index 0000000..5bd220b --- /dev/null +++ b/src/3.asm @@ -0,0 +1,44 @@ +; FV-1 Testing Bank +; +; Check behaviour of FV-1 against documentation +; + +; Program 3 : Check WRAX/LDAX +; +; Expected output: max (pass) or min (fail) + +; Immediates +equ chkhi 0xaaaaaa ; test pattern one +equ chklo 0x555555 ; test pattern two +equ maxval 0x7fffff ; maximum immediate value +equ minval 0x800000 ; minimim immediate value + +; Registers +equ CHK REG0 ; register to hold check val + +test1: clr + or chkhi + wrax CHK,1.0 ; write immediate to register + or 0xffffff ; set all bits + ldax CHK ; move check value into ACC + xor chkhi ; compare with required value + skp ZRO,test2 ; if same, continue + clr + skp ZRO,fail ; else skip to fail + +test2: clr + or chklo + wrax CHK,1.0 + or 0xffffff + ldax CHK + xor chklo + skp ZRO,pass ; both tests ok + +fail: clr + or minval ; write fail flag + wrax DACL,0.0 ; output to DAC + skp ZRO,end +pass: clr + or maxval ; write pass flag + wrax DACL,0.0 ; output to DAC +end: nop diff --git a/src/4.asm b/src/4.asm new file mode 100644 index 0000000..3cac96c --- /dev/null +++ b/src/4.asm @@ -0,0 +1,49 @@ +; FV-1 Testing Bank +; +; Check behaviour of FV-1 against documentation +; + +; Program 4 : Output Range +; +; Manually sweep output over all values +; +; Expected output: sawtooth with period 2**24/fs (~512s) + +; Waveform parameters +equ maxval 0x7fffff ; ACC maximum +equ minval 0x800000 ; ACC minimum +equ incval 0x1 ; per sample increment + +; Registers +equ PREV REG0 ; last output +equ CUR REG1 ; next output +equ MAX REG3 ; reg to store maxval +equ MIN REG4 ; reg ro store minval +equ INC REG5 ; reg to store incval + +; Prepare constants + skp RUN,main + clr + or maxval + wrax MAX,0.0 + or minval + wrax MIN,0.0 + or incval + wrax INC,0.0 + +main: ldax PREV ; read previous output + xor maxval ; compare with maximum value + skp ZRO,tomin ; if PREV was as max, change to MIN + +incr: ldax INC ; load increment into ACC + rdax PREV,1.0 ; load acc with PREV + INC + wrax CUR,0.0 ; store to CUR and clear ACC + skp ZRO,output ; skip to output + +tomin: ldax MIN ; load minimum val into ACC + wrax CUR,0.0 ; store minimum in CUR and clear ACC + skp ZRO,output ; skip to output + +output: ldax CUR ; load the computed value into ACC + wrax PREV,1.0 ; store value in PREV register + wrax DACL,0.0 ; output value to DAC diff --git a/src/5.asm b/src/5.asm new file mode 100644 index 0000000..eeb5d37 --- /dev/null +++ b/src/5.asm @@ -0,0 +1,14 @@ +; FV-1 Testing Bank +; +; Check behaviour of FV-1 against documentation +; + +; Program 5 : PACC Init Val +; +; Expected output: 0.0 + + skp RUN,output + wrlx REG0,0.0 ; copy PACC into ACC + wrax REG1,0.0 +output: ldax REG1 + wrax DACL,0.0 ; output stored value diff --git a/src/6.asm b/src/6.asm new file mode 100644 index 0000000..458be9f --- /dev/null +++ b/src/6.asm @@ -0,0 +1,20 @@ +; FV-1 Testing Bank A +; +; Check behaviour of FV-1 against documentation +; + +; Program 6 : ACC Init Val +; +; note: also copies ADCL into delay for use with program 7 +; +; Expected output: 0.0 + +mem delay 1 + + skp RUN,output + wrax REG1,0.0 ; store ACC init value +output: ldax REG1 + wrax DACL,0.0 + ldax ADCL + wra delay,1.0 + wrax DACR,0.0 diff --git a/src/7.asm b/src/7.asm new file mode 100644 index 0000000..41b569a --- /dev/null +++ b/src/7.asm @@ -0,0 +1,14 @@ +; FV-1 Testing Bank A +; +; Check behaviour of FV-1 against documentation +; + +; Program 7 : Delay Init Val +; +; Expected output: 0.0 + +mem delay 1 + + clr + rda delay,1.0 ; read from empty delay + wrax DACL,0.0