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@ -157,7 +157,7 @@ static inline void oper_move_relative_or_explode(Gbuffer gbuf, Mbuffer mbuf, |
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if (!Dual_is_active) \ |
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if (!Dual_is_active) \ |
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return |
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return |
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#define INPUT_PORT(_delta_y, _delta_x, _flags) \ |
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#define I_PORT(_delta_y, _delta_x, _flags) \ |
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mbuffer_poke_relative_flags_or( \ |
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mbuffer_poke_relative_flags_or( \ |
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mbuffer, height, width, y, x, _delta_y, _delta_x, \ |
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mbuffer, height, width, y, x, _delta_y, _delta_x, \ |
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Mark_flag_input | ((_flags)&Mark_flag_haste_input) | \ |
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Mark_flag_input | ((_flags)&Mark_flag_haste_input) | \ |
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@ -165,7 +165,7 @@ static inline void oper_move_relative_or_explode(Gbuffer gbuf, Mbuffer mbuf, |
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(cell_flags & (Mark_flag_lock | Mark_flag_sleep)) \ |
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(cell_flags & (Mark_flag_lock | Mark_flag_sleep)) \ |
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? Mark_flag_none \ |
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? Mark_flag_none \ |
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: (_flags))) |
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: (_flags))) |
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#define OUTPUT_PORT(_delta_y, _delta_x, _flags) \ |
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#define O_PORT(_delta_y, _delta_x, _flags) \ |
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mbuffer_poke_relative_flags_or( \ |
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mbuffer_poke_relative_flags_or( \ |
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mbuffer, height, width, y, x, _delta_y, _delta_x, \ |
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mbuffer, height, width, y, x, _delta_y, _delta_x, \ |
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Mark_flag_input | ((_flags)&Mark_flag_haste_input) | \ |
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Mark_flag_input | ((_flags)&Mark_flag_haste_input) | \ |
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@ -218,9 +218,9 @@ OPER_DEFINE_DIRECTIONAL(west, 0, -1) |
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BEGIN_DUAL_PHASE_0(add) |
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BEGIN_DUAL_PHASE_0(add) |
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REALIZE_DUAL; |
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REALIZE_DUAL; |
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BEGIN_DUAL_PORTS |
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BEGIN_DUAL_PORTS |
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INPUT_PORT(0, 1, PORT_LOCKED); |
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I_PORT(0, 1, PORT_LOCKED); |
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INPUT_PORT(0, 2, PORT_LOCKED); |
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I_PORT(0, 2, PORT_LOCKED); |
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OUTPUT_PORT(1, 0, PORT_LOCKED); |
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O_PORT(1, 0, PORT_LOCKED); |
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END_PORTS |
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END_PORTS |
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END_PHASE |
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END_PHASE |
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BEGIN_DUAL_PHASE_1(add) |
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BEGIN_DUAL_PHASE_1(add) |
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@ -235,9 +235,9 @@ END_PHASE |
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BEGIN_DUAL_PHASE_0(modulo) |
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BEGIN_DUAL_PHASE_0(modulo) |
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REALIZE_DUAL; |
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REALIZE_DUAL; |
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BEGIN_DUAL_PORTS |
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BEGIN_DUAL_PORTS |
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INPUT_PORT(0, 1, PORT_LOCKED); |
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I_PORT(0, 1, PORT_LOCKED); |
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INPUT_PORT(0, 2, PORT_LOCKED); |
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I_PORT(0, 2, PORT_LOCKED); |
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OUTPUT_PORT(1, 0, PORT_LOCKED); |
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O_PORT(1, 0, PORT_LOCKED); |
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END_PORTS |
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END_PORTS |
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END_PHASE |
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END_PHASE |
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BEGIN_DUAL_PHASE_1(modulo) |
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BEGIN_DUAL_PHASE_1(modulo) |
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@ -252,9 +252,9 @@ END_PHASE |
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BEGIN_DUAL_PHASE_0(increment) |
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BEGIN_DUAL_PHASE_0(increment) |
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REALIZE_DUAL; |
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REALIZE_DUAL; |
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BEGIN_DUAL_PORTS |
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BEGIN_DUAL_PORTS |
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INPUT_PORT(0, 1, PORT_LOCKED); |
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I_PORT(0, 1, PORT_LOCKED); |
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INPUT_PORT(0, 2, PORT_LOCKED); |
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I_PORT(0, 2, PORT_LOCKED); |
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OUTPUT_PORT(1, 0, PORT_LOCKED); |
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O_PORT(1, 0, PORT_LOCKED); |
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END_PORTS |
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END_PORTS |
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END_PHASE |
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END_PHASE |
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BEGIN_DUAL_PHASE_1(increment) |
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BEGIN_DUAL_PHASE_1(increment) |
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