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/**
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****************************************************************************** |
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* @file stm32f4xx_hal_can_legacy.h |
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* @author MCD Application Team |
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* @brief Header file of CAN HAL module. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2016 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F4xx_HAL_CAN_LEGACY_H |
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#define __STM32F4xx_HAL_CAN_LEGACY_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
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defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
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defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ |
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defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ |
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defined(STM32F423xx) |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f4xx_hal_def.h" |
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{ |
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*/ |
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/** @addtogroup CAN
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* @{ |
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*/ |
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/* Exported types ------------------------------------------------------------*/ |
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/** @defgroup CAN_Exported_Types CAN Exported Types
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* @{ |
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*/ |
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/**
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* @brief HAL State structures definition |
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*/ |
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typedef enum |
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{ |
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HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ |
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HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ |
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HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ |
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HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ |
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HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ |
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}HAL_CAN_StateTypeDef; |
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/**
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* @brief CAN init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t Prescaler; /*!< Specifies the length of a time quantum.
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This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
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uint32_t Mode; /*!< Specifies the CAN operating mode.
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This parameter can be a value of @ref CAN_operating_mode */ |
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uint32_t SJW; /*!< Specifies the maximum number of time quanta
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the CAN hardware is allowed to lengthen or |
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shorten a bit to perform resynchronization. |
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This parameter can be a value of @ref CAN_synchronisation_jump_width */ |
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uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ |
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uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ |
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uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
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This parameter can be set to ENABLE or DISABLE */ |
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uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
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This parameter can be set to ENABLE or DISABLE */ |
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uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
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This parameter can be set to ENABLE or DISABLE */ |
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uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
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This parameter can be set to ENABLE or DISABLE */ |
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uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
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This parameter can be set to ENABLE or DISABLE */ |
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}CAN_InitTypeDef; |
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/**
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* @brief CAN filter configuration structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
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configuration, first one for a 16-bit configuration). |
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
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configuration, second one for a 16-bit configuration). |
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
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according to the mode (MSBs for a 32-bit configuration, |
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first one for a 16-bit configuration). |
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
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according to the mode (LSBs for a 32-bit configuration, |
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second one for a 16-bit configuration). |
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
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uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
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This parameter can be a value of @ref CAN_filter_FIFO */ |
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uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
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This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ |
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uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
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This parameter can be a value of @ref CAN_filter_mode */ |
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uint32_t FilterScale; /*!< Specifies the filter scale.
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This parameter can be a value of @ref CAN_filter_scale */ |
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uint32_t FilterActivation; /*!< Enable or disable the filter.
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t BankNumber; /*!< Select the start slave bank filter.
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This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ |
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}CAN_FilterConfTypeDef; |
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/**
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* @brief CAN Tx message structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ |
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ |
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
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This parameter can be a value of @ref CAN_Identifier_Type */ |
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uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
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This parameter can be a value of @ref CAN_remote_transmission_request */ |
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uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ |
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uint8_t Data[8]; /*!< Contains the data to be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
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}CanTxMsgTypeDef; |
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/**
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* @brief CAN Rx message structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ |
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ |
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
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This parameter can be a value of @ref CAN_Identifier_Type */ |
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uint32_t RTR; /*!< Specifies the type of frame for the received message.
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This parameter can be a value of @ref CAN_remote_transmission_request */ |
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uint32_t DLC; /*!< Specifies the length of the frame that will be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ |
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uint8_t Data[8]; /*!< Contains the data to be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
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uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
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uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
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This parameter can be CAN_FIFO0 or CAN_FIFO1 */ |
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}CanRxMsgTypeDef; |
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/**
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* @brief CAN handle Structure definition |
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*/ |
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typedef struct |
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{ |
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CAN_TypeDef *Instance; /*!< Register base address */ |
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CAN_InitTypeDef Init; /*!< CAN required parameters */ |
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CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ |
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CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ |
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CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ |
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__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ |
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HAL_LockTypeDef Lock; /*!< CAN locking object */ |
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__IO uint32_t ErrorCode; /*!< CAN Error code */ |
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}CAN_HandleTypeDef; |
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/**
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* @} |
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*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/** @defgroup CAN_Exported_Constants CAN Exported Constants
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* @{ |
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*/ |
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/** @defgroup CAN_Error_Code CAN Error Code
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* @{ |
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*/ |
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#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ |
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#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ |
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#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ |
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#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ |
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#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ |
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#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ |
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#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ |
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#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ |
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#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ |
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#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ |
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#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ |
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#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ |
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#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_InitStatus CAN InitStatus
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* @{ |
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*/ |
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#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ |
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#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_operating_mode CAN Operating Mode
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* @{ |
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*/ |
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#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ |
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#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ |
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#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ |
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#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
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* @{ |
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*/ |
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#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ |
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#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ |
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#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ |
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#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
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* @{ |
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*/ |
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#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ |
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#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ |
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#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ |
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#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ |
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#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ |
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#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ |
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#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ |
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#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ |
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#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ |
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#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ |
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#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ |
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#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ |
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#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ |
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#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ |
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#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ |
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#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
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* @{ |
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*/ |
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#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ |
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#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ |
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#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ |
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#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ |
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#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ |
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#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ |
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#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ |
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#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_filter_mode CAN Filter Mode
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* @{ |
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*/ |
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#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ |
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#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_filter_scale CAN Filter Scale
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* @{ |
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*/ |
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#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ |
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#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_filter_FIFO CAN Filter FIFO
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* @{ |
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*/ |
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#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ |
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#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_Identifier_Type CAN Identifier Type
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* @{ |
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*/ |
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#define CAN_ID_STD 0x00000000U /*!< Standard Id */ |
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#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
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* @{ |
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*/ |
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#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ |
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#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
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* @{ |
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*/ |
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#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ |
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#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_flags CAN Flags
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* @{ |
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*/ |
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/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
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and CAN_ClearFlag() functions. */ |
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/* If the flag is 0x1XXXXXXX, it means that it can only be used with
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CAN_GetFlagStatus() function. */ |
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/* Transmit Flags */ |
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#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ |
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#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ |
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#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ |
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#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ |
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#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ |
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#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ |
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#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ |
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#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ |
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#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ |
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/* Receive Flags */ |
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#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ |
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#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ |
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#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ |
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#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ |
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/* Operating Mode Flags */ |
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#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ |
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#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ |
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#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ |
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#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ |
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#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ |
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/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
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In this case the SLAK bit can be polled.*/ |
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/* Error Flags */ |
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#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ |
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#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ |
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#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ |
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/**
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* @} |
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*/ |
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/** @defgroup CAN_Interrupts CAN Interrupts
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* @{ |
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*/ |
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#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ |
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/* Receive Interrupts */ |
|||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ |
|||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ |
|||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ |
|||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ |
|||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ |
|||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ |
|||
|
|||
/* Operating Mode Interrupts */ |
|||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ |
|||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ |
|||
|
|||
/* Error Interrupts */ |
|||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ |
|||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ |
|||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ |
|||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ |
|||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
|
|||
* @{ |
|||
*/ |
|||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00) |
|||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01) |
|||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset CAN handle state
|
|||
* @param __HANDLE__ specifies the CAN Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) |
|||
|
|||
/**
|
|||
* @brief Enable the specified CAN interrupts. |
|||
* @param __HANDLE__ CAN handle |
|||
* @param __INTERRUPT__ CAN Interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the specified CAN interrupts. |
|||
* @param __HANDLE__ CAN handle |
|||
* @param __INTERRUPT__ CAN Interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Return the number of pending received messages. |
|||
* @param __HANDLE__ CAN handle |
|||
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
|||
* @retval The number of pending message. |
|||
*/ |
|||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ |
|||
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) |
|||
|
|||
/** @brief Check whether the specified CAN flag is set or not.
|
|||
* @param __HANDLE__ CAN Handle |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag |
|||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag |
|||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag |
|||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag |
|||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag |
|||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag |
|||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag |
|||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag |
|||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag |
|||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag |
|||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag |
|||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag |
|||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag |
|||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag |
|||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag |
|||
* @arg CAN_FLAG_WKU: Wake up Flag |
|||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag |
|||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag |
|||
* @arg CAN_FLAG_EWG: Error Warning Flag |
|||
* @arg CAN_FLAG_EPV: Error Passive Flag |
|||
* @arg CAN_FLAG_BOF: Bus-Off Flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ |
|||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) |
|||
|
|||
/** @brief Clear the specified CAN pending flag.
|
|||
* @param __HANDLE__ CAN Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag |
|||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag |
|||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag |
|||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag |
|||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag |
|||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag |
|||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag |
|||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag |
|||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag |
|||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag |
|||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag |
|||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag |
|||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag |
|||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag |
|||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag |
|||
* @arg CAN_FLAG_WKU: Wake up Flag |
|||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag |
|||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
|||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) |
|||
|
|||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ CAN Handle |
|||
* @param __INTERRUPT__ specifies the CAN interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
|||
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable |
|||
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/**
|
|||
* @brief Check the transmission status of a CAN Frame. |
|||
* @param __HANDLE__ CAN Handle |
|||
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. |
|||
* @retval The new status of transmission (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ |
|||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ |
|||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ |
|||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) |
|||
|
|||
/**
|
|||
* @brief Release the specified receive FIFO. |
|||
* @param __HANDLE__ CAN handle |
|||
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ |
|||
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) |
|||
|
|||
/**
|
|||
* @brief Cancel a transmit request. |
|||
* @param __HANDLE__ CAN Handle |
|||
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ |
|||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ |
|||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ |
|||
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) |
|||
|
|||
/**
|
|||
* @brief Enable or disable the DBG Freeze for CAN. |
|||
* @param __HANDLE__ CAN Handle |
|||
* @param __NEWSTATE__ new state of the CAN peripheral. |
|||
* This parameter can be: ENABLE (CAN reception/transmission is frozen |
|||
* during debug. Reception FIFOs can still be accessed/controlled normally) |
|||
* or DISABLE (CAN is working during debug). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ |
|||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup CAN_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); |
|||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); |
|||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); |
|||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); |
|||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); |
|||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); |
|||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); |
|||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); |
|||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ***************************************************/ |
|||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); |
|||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Types CAN Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ |
|||
#define CAN_FLAG_MASK 0x000000FFU |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ |
|||
((MODE) == CAN_MODE_LOOPBACK)|| \ |
|||
((MODE) == CAN_MODE_SILENT) || \ |
|||
((MODE) == CAN_MODE_SILENT_LOOPBACK)) |
|||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ |
|||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) |
|||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) |
|||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) |
|||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) |
|||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) |
|||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ |
|||
((MODE) == CAN_FILTERMODE_IDLIST)) |
|||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ |
|||
((SCALE) == CAN_FILTERSCALE_32BIT)) |
|||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ |
|||
((FIFO) == CAN_FILTER_FIFO1)) |
|||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) |
|||
|
|||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) |
|||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) |
|||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) |
|||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) |
|||
|
|||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ |
|||
((IDTYPE) == CAN_ID_EXT)) |
|||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) |
|||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Functions CAN Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
|||
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ |
|||
STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */ |
|||
File diff suppressed because it is too large
@ -0,0 +1,56 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32_assert.h |
|||
* @author MCD Application Team |
|||
* @brief STM32 assert template file. |
|||
* This file should be copied to the application folder and renamed |
|||
* to stm32_assert.h. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32_ASSERT_H |
|||
#define __STM32_ASSERT_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
#ifdef USE_FULL_ASSERT |
|||
/**
|
|||
* @brief The assert_param macro is used for function's parameters check. |
|||
* @param expr If expr is false, it calls assert_failed function |
|||
* which reports the name of the source file and the source |
|||
* line number of the call that failed. |
|||
* If expr is true, it returns no value. |
|||
* @retval None |
|||
*/ |
|||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
|||
/* Exported functions ------------------------------------------------------- */ |
|||
void assert_failed(uint8_t* file, uint32_t line); |
|||
#else |
|||
#define assert_param(expr) ((void)0U) |
|||
#endif /* USE_FULL_ASSERT */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32_ASSERT_H */ |
|||
|
|||
|
|||
|
|||
@ -0,0 +1,898 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_adc.h |
|||
* @author MCD Application Team |
|||
* @brief Header file containing functions prototypes of ADC HAL library. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_ADC_H |
|||
#define __STM32F4xx_ADC_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/* Include low level driver */ |
|||
#include "stm32f4xx_ll_adc.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADC
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Types ADC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Structure definition of ADC and regular group initialization |
|||
* @note Parameters of this structure are shared within 2 scopes: |
|||
* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. |
|||
* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. |
|||
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
|||
* ADC state can be either: |
|||
* - For all parameters: ADC disabled |
|||
* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. |
|||
* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. |
|||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
|||
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
|
|||
all the ADCs. |
|||
This parameter can be a value of @ref ADC_ClockPrescaler */ |
|||
uint32_t Resolution; /*!< Configures the ADC resolution.
|
|||
This parameter can be a value of @ref ADC_Resolution */ |
|||
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
|
|||
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). |
|||
This parameter can be a value of @ref ADC_Data_align */ |
|||
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
|
|||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
|||
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). |
|||
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). |
|||
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). |
|||
Scan direction is upward: from rank1 to rank 'n'. |
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
|
|||
This parameter can be a value of @ref ADC_EOCSelection. |
|||
Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. |
|||
Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) |
|||
or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. |
|||
Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). |
|||
If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ |
|||
FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
|
|||
after the selected trigger occurred (software start or external trigger). |
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
|
|||
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
|||
FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
|||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
|||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
|
|||
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
|||
uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
|
|||
If set to ADC_SOFTWARE_START, external triggers are disabled. |
|||
If set to external trigger source, triggering is on event rising edge by default. |
|||
This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ |
|||
uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
|
|||
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. |
|||
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
|||
FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
|
|||
or in Continuous mode (DMA transfer unlimited, whatever number of conversions). |
|||
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. |
|||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). |
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
} ADC_InitTypeDef; |
|||
|
|||
|
|||
|
|||
/**
|
|||
* @brief Structure definition of ADC channel for regular group |
|||
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
|||
* ADC can be either disabled or enabled without conversion on going on regular group. |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
|
|||
This parameter can be a value of @ref ADC_channels */ |
|||
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
|||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
|||
Unit: ADC clock cycles |
|||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). |
|||
This parameter can be a value of @ref ADC_sampling_times |
|||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
|||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
|||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
|||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
|||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ |
|||
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ |
|||
} ADC_ChannelConfTypeDef; |
|||
|
|||
/**
|
|||
* @brief ADC Configuration multi-mode structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
|
|||
This parameter can be a value of @ref ADC_analog_watchdog_selection */ |
|||
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
|||
This parameter must be a 12-bit value. */ |
|||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
|||
This parameter must be a 12-bit value. */ |
|||
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
|
|||
This parameter has an effect only if watchdog mode is configured on single channel |
|||
This parameter can be a value of @ref ADC_channels */ |
|||
FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
|
|||
is interrupt mode or in polling mode. |
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
|||
} ADC_AnalogWDGConfTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL ADC state machine: ADC states definition (bitfields) |
|||
*/ |
|||
/* States of ADC global scope */ |
|||
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ |
|||
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ |
|||
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ |
|||
#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ |
|||
|
|||
/* States of ADC errors */ |
|||
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ |
|||
#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ |
|||
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ |
|||
|
|||
/* States of ADC group regular */ |
|||
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, |
|||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ |
|||
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ |
|||
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ |
|||
|
|||
/* States of ADC group injected */ |
|||
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
|||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ |
|||
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ |
|||
|
|||
/* States of ADC analog watchdogs */ |
|||
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ |
|||
#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */ |
|||
#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */ |
|||
|
|||
/* States of ADC multi-mode */ |
|||
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ |
|||
|
|||
|
|||
/**
|
|||
* @brief ADC handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
typedef struct __ADC_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif |
|||
{ |
|||
ADC_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
ADC_InitTypeDef Init; /*!< ADC required parameters */ |
|||
|
|||
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ |
|||
|
|||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< ADC locking object */ |
|||
|
|||
__IO uint32_t State; /*!< ADC communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< ADC Error code */ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ |
|||
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ |
|||
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ |
|||
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ |
|||
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ |
|||
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ |
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
} ADC_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL ADC Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ |
|||
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ |
|||
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ |
|||
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ |
|||
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ |
|||
HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ |
|||
HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ |
|||
} HAL_ADC_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL ADC Callback pointer definition |
|||
*/ |
|||
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ |
|||
|
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Error_Code ADC Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ |
|||
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, |
|||
enable/disable, erroneous state */ |
|||
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ |
|||
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
|
|||
* @{ |
|||
*/ |
|||
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U |
|||
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) |
|||
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) |
|||
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) |
|||
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) |
|||
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) |
|||
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Resolution ADC Resolution
|
|||
* @{ |
|||
*/ |
|||
#define ADC_RESOLUTION_12B 0x00000000U |
|||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) |
|||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) |
|||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U |
|||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
|
|||
* @{ |
|||
*/ |
|||
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ |
|||
/* compatibility with other STM32 devices. */ |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) |
|||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) |
|||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) |
|||
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Data_align ADC Data Align
|
|||
* @{ |
|||
*/ |
|||
#define ADC_DATAALIGN_RIGHT 0x00000000U |
|||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_channels ADC Common Channels
|
|||
* @{ |
|||
*/ |
|||
#define ADC_CHANNEL_0 0x00000000U |
|||
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) |
|||
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) |
|||
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) |
|||
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) |
|||
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) |
|||
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) |
|||
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) |
|||
|
|||
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) |
|||
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_sampling_times ADC Sampling Times
|
|||
* @{ |
|||
*/ |
|||
#define ADC_SAMPLETIME_3CYCLES 0x00000000U |
|||
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) |
|||
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) |
|||
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) |
|||
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) |
|||
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) |
|||
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) |
|||
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_EOCSelection ADC EOC Selection
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EOC_SEQ_CONV 0x00000000U |
|||
#define ADC_EOC_SINGLE_CONV 0x00000001U |
|||
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Event_type ADC Event Type
|
|||
* @{ |
|||
*/ |
|||
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
|||
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
|||
* @{ |
|||
*/ |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) |
|||
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) |
|||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
|||
* @{ |
|||
*/ |
|||
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) |
|||
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) |
|||
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) |
|||
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_flags_definition ADC Flags Definition
|
|||
* @{ |
|||
*/ |
|||
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) |
|||
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) |
|||
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) |
|||
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) |
|||
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) |
|||
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_channels_type ADC Channels Type
|
|||
* @{ |
|||
*/ |
|||
#define ADC_ALL_CHANNELS 0x00000001U |
|||
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ |
|||
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset ADC handle state
|
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
|||
do{ \ |
|||
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
|||
((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
|||
#endif |
|||
|
|||
/**
|
|||
* @brief Enable the ADC peripheral. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) |
|||
|
|||
/**
|
|||
* @brief Disable the ADC peripheral. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC end of conversion interrupt. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __INTERRUPT__ ADC Interrupt. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the ADC end of conversion interrupt. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __INTERRUPT__ ADC interrupt. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) |
|||
|
|||
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __INTERRUPT__ specifies the ADC interrupt source to check. |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Clear the ADC's pending flags. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __FLAG__ ADC flag. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Get the selected ADC's flag status. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __FLAG__ ADC flag. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include ADC HAL Extension module */ |
|||
#include "stm32f4xx_hal_adc_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADC_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); |
|||
|
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); |
|||
|
|||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); |
|||
|
|||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); |
|||
|
|||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); |
|||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group4
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ***************************************************/ |
|||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); |
|||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Constants ADC Private Constants
|
|||
* @{ |
|||
*/ |
|||
/* Delay for ADC stabilization time. */ |
|||
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
|||
/* Unit: us */ |
|||
#define ADC_STAB_DELAY_US 3U |
|||
/* Delay for temperature sensor stabilization time. */ |
|||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
|||
/* Unit: us */ |
|||
#define ADC_TEMPSENSOR_DELAY_US 10U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macro ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
|||
* @{ |
|||
*/ |
|||
/* Macro reserved for internal HAL driver usage, not intended to be used in
|
|||
code of final user */ |
|||
|
|||
/**
|
|||
* @brief Verification of ADC state: enabled or disabled |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval SET (ADC enabled) or RESET (ADC disabled) |
|||
*/ |
|||
#define ADC_IS_ENABLE(__HANDLE__) \ |
|||
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ |
|||
) ? SET : RESET) |
|||
|
|||
/**
|
|||
* @brief Test if conversion trigger of regular group is software start |
|||
* or external trigger. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval SET (software start) or RESET (external trigger) |
|||
*/ |
|||
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
|||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) |
|||
|
|||
/**
|
|||
* @brief Test if conversion trigger of injected group is software start |
|||
* or external trigger. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval SET (software start) or RESET (external trigger) |
|||
*/ |
|||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ |
|||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) |
|||
|
|||
/**
|
|||
* @brief Simultaneously clears and sets specific bits of the handle State |
|||
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
|||
* the first parameter is the ADC handle State, the second parameter is the |
|||
* bit field to clear, the third and last parameter is the bit field to set. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_STATE_CLR_SET MODIFY_REG |
|||
|
|||
/**
|
|||
* @brief Clear ADC error code (set it to error code: "no error") |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
|||
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
|||
|
|||
|
|||
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
|||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ |
|||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ |
|||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) |
|||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) |
|||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_10B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_6B)) |
|||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) |
|||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ |
|||
((REGTRIG) == ADC_SOFTWARE_START)) |
|||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
|||
((ALIGN) == ADC_DATAALIGN_LEFT)) |
|||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_15CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_28CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_56CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_84CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_112CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_144CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_480CYCLES)) |
|||
#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ |
|||
((EOCSelection) == ADC_EOC_SEQ_CONV) || \ |
|||
((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) |
|||
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ |
|||
((EVENT) == ADC_OVR_EVENT)) |
|||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) |
|||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ |
|||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ |
|||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) |
|||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) |
|||
|
|||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) |
|||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) |
|||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) |
|||
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
|||
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) |
|||
|
|||
/**
|
|||
* @brief Set ADC Regular channel sequence length. |
|||
* @param _NbrOfConversion_ Regular channel sequence length. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) |
|||
|
|||
/**
|
|||
* @brief Set the ADC's sample time for channel numbers between 10 and 18. |
|||
* @param _SAMPLETIME_ Sample time parameter. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) |
|||
|
|||
/**
|
|||
* @brief Set the ADC's sample time for channel numbers between 0 and 9. |
|||
* @param _SAMPLETIME_ Sample time parameter. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) |
|||
|
|||
/**
|
|||
* @brief Set the selected regular channel rank for rank between 1 and 6. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) |
|||
|
|||
/**
|
|||
* @brief Set the selected regular channel rank for rank between 7 and 12. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) |
|||
|
|||
/**
|
|||
* @brief Set the selected regular channel rank for rank between 13 and 16. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) |
|||
|
|||
/**
|
|||
* @brief Enable ADC continuous conversion mode. |
|||
* @param _CONTINUOUS_MODE_ Continuous mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) |
|||
|
|||
/**
|
|||
* @brief Configures the number of discontinuous conversions for the regular group channels. |
|||
* @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) |
|||
|
|||
/**
|
|||
* @brief Enable ADC scan mode. |
|||
* @param _SCANCONV_MODE_ Scan conversion mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC end of conversion selection. |
|||
* @param _EOCSelection_MODE_ End of conversion selection mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC DMA continuous request. |
|||
* @param _DMAContReq_MODE_ DMA continuous request mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) |
|||
|
|||
/**
|
|||
* @brief Return resolution bits in CR1 register. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Functions ADC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /*__STM32F4xx_ADC_H */ |
|||
|
|||
|
|||
@ -0,0 +1,407 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_adc_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of ADC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_ADC_EX_H |
|||
#define __STM32F4xx_ADC_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADCEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Exported_Types ADC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief ADC Configuration injected Channel structure definition |
|||
* @note Parameters of this structure are shared within 2 scopes: |
|||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset |
|||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, |
|||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. |
|||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. |
|||
* ADC state can be either: |
|||
* - For all parameters: ADC disabled |
|||
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. |
|||
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
|||
This parameter can be a value of @ref ADC_channels |
|||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
|||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
|||
This parameter must be a value of @ref ADCEx_injected_rank |
|||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
|||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
|||
Unit: ADC clock cycles |
|||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). |
|||
This parameter can be a value of @ref ADC_sampling_times |
|||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
|||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
|||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
|||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
|||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ |
|||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
|||
Offset value must be a positive number. |
|||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
|||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
|||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
|||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 4. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
|||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
|||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
|||
This parameter can be set to ENABLE or DISABLE. |
|||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
|||
This parameter can be set to ENABLE or DISABLE. |
|||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) |
|||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) |
|||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. |
|||
To maintain JAUTO always enabled, DMA must be configured in circular mode. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
|||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. |
|||
If set to external trigger source, triggering is on event rising edge. |
|||
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected |
|||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). |
|||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
|||
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. |
|||
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
} ADC_InjectionConfTypeDef; |
|||
|
|||
/**
|
|||
* @brief ADC Configuration multi-mode structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
|||
This parameter can be a value of @ref ADCEx_Common_mode */ |
|||
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
|||
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ |
|||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
|||
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ |
|||
} ADC_MultiModeTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_Common_mode ADC Common Mode
|
|||
* @{ |
|||
*/ |
|||
#define ADC_MODE_INDEPENDENT 0x00000000U |
|||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) |
|||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) |
|||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) |
|||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) |
|||
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) |
|||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) |
|||
#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) |
|||
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
|
|||
* @{ |
|||
*/ |
|||
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */ |
|||
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ |
|||
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ |
|||
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U |
|||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL) |
|||
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_injected_rank ADC Injected Rank
|
|||
* @{ |
|||
*/ |
|||
#define ADC_INJECTED_RANK_1 0x00000001U |
|||
#define ADC_INJECTED_RANK_2 0x00000002U |
|||
#define ADC_INJECTED_RANK_3 0x00000003U |
|||
#define ADC_INJECTED_RANK_4 0x00000004U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_channels ADC Specific Channels
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
|||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ |
|||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ |
|||
defined(STM32F412Cx) |
|||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || |
|||
STM32F412Vx || STM32F412Rx || STM32F412Cx */ |
|||
|
|||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
|||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ |
|||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) |
|||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
|||
/**
|
|||
* @brief Disable internal path of ADC channel Vbat |
|||
* @note Use case of this macro: |
|||
* On devices STM32F42x and STM32F43x, ADC internal channels |
|||
* Vbat and VrefInt share the same internal path, only |
|||
* one of them can be enabled.This macro is to be used when ADC |
|||
* channels Vbat and VrefInt are selected, and must be called |
|||
* before starting conversion of ADC channel VrefInt in order |
|||
* to disable ADC channel Vbat. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE)) |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADCEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); |
|||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); |
|||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); |
|||
|
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Constants ADC Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Macros ADC Private Macros
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
|||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ |
|||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ |
|||
defined(STM32F412Cx) |
|||
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || |
|||
STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ |
|||
|
|||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \ |
|||
defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \ |
|||
defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ |
|||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) |
|||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
|
|||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ |
|||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_INTERL) || \ |
|||
((MODE) == ADC_DUALMODE_ALTERTRIG) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ |
|||
((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_INTERL) || \ |
|||
((MODE) == ADC_TRIPLEMODE_ALTERTRIG)) |
|||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_1) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_2) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_3)) |
|||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) |
|||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \ |
|||
((INJTRIG) == ADC_INJECTED_SOFTWARE_START)) |
|||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) |
|||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U)) |
|||
|
|||
/**
|
|||
* @brief Set the selected injected Channel rank. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @param _JSQR_JL_ Sequence length. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_)))) |
|||
|
|||
/**
|
|||
* @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1 |
|||
* if available (ADC2, ADC3 availability depends on STM32 product) |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval Common control register ADC123 or ADC1 |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON |
|||
#else |
|||
#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON |
|||
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Functions ADC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /*__STM32F4xx_ADC_EX_H */ |
|||
|
|||
|
|||
@ -0,0 +1,853 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_can.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of CAN HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_CAN_H |
|||
#define STM32F4xx_HAL_CAN_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (CAN1) |
|||
/** @addtogroup CAN
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ |
|||
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ |
|||
HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ |
|||
HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ |
|||
HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ |
|||
HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ |
|||
|
|||
} HAL_CAN_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ |
|||
|
|||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
|||
This parameter can be a value of @ref CAN_operating_mode */ |
|||
|
|||
uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
|
|||
is allowed to lengthen or shorten a bit to perform resynchronization. |
|||
This parameter can be a value of @ref CAN_synchronisation_jump_width */ |
|||
|
|||
uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
|||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ |
|||
|
|||
uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
|||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ |
|||
|
|||
FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
} CAN_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN filter configuration structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
|||
configuration, first one for a 16-bit configuration). |
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
|||
|
|||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
|||
configuration, second one for a 16-bit configuration). |
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
|||
|
|||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
|||
according to the mode (MSBs for a 32-bit configuration, |
|||
first one for a 16-bit configuration). |
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
|||
|
|||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
|||
according to the mode (LSBs for a 32-bit configuration, |
|||
second one for a 16-bit configuration). |
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
|||
|
|||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
|
|||
This parameter can be a value of @ref CAN_filter_FIFO */ |
|||
|
|||
uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
|
|||
For single CAN instance(14 dedicated filter banks), |
|||
this parameter must be a number between Min_Data = 0 and Max_Data = 13. |
|||
For dual CAN instances(28 filter banks shared), |
|||
this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ |
|||
|
|||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
|||
This parameter can be a value of @ref CAN_filter_mode */ |
|||
|
|||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
|||
This parameter can be a value of @ref CAN_filter_scale */ |
|||
|
|||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
|||
This parameter can be a value of @ref CAN_filter_activation */ |
|||
|
|||
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
|
|||
For single CAN instances, this parameter is meaningless. |
|||
For dual CAN instances, all filter banks with lower index are assigned to master |
|||
CAN instance, whereas all filter banks with greater index are assigned to slave |
|||
CAN instance. |
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ |
|||
|
|||
} CAN_FilterTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN Tx message header structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t StdId; /*!< Specifies the standard identifier.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ |
|||
|
|||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
|||
This parameter can be a value of @ref CAN_identifier_type */ |
|||
|
|||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
|||
This parameter can be a value of @ref CAN_remote_transmission_request */ |
|||
|
|||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ |
|||
|
|||
FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
|
|||
of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. |
|||
@note: Time Triggered Communication Mode must be enabled. |
|||
@note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. |
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
} CAN_TxHeaderTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN Rx message header structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t StdId; /*!< Specifies the standard identifier.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ |
|||
|
|||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
|||
This parameter can be a value of @ref CAN_identifier_type */ |
|||
|
|||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
|||
This parameter can be a value of @ref CAN_remote_transmission_request */ |
|||
|
|||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ |
|||
|
|||
uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
|
|||
@note: Time Triggered Communication Mode must be enabled. |
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ |
|||
|
|||
uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ |
|||
|
|||
} CAN_RxHeaderTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN handle Structure definition |
|||
*/ |
|||
typedef struct __CAN_HandleTypeDef |
|||
{ |
|||
CAN_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
CAN_InitTypeDef Init; /*!< CAN required parameters */ |
|||
|
|||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< CAN Error code.
|
|||
This parameter can be a value of @ref CAN_Error_Code */ |
|||
|
|||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 |
|||
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ |
|||
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ |
|||
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ |
|||
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ |
|||
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ |
|||
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ |
|||
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ |
|||
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ |
|||
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ |
|||
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ |
|||
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ |
|||
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ |
|||
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ |
|||
|
|||
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ |
|||
|
|||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ |
|||
} CAN_HandleTypeDef; |
|||
|
|||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 |
|||
/**
|
|||
* @brief HAL CAN common Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ |
|||
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ |
|||
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ |
|||
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ |
|||
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ |
|||
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ |
|||
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ |
|||
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ |
|||
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ |
|||
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ |
|||
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ |
|||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ |
|||
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ |
|||
|
|||
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ |
|||
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ |
|||
|
|||
} HAL_CAN_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL CAN Callback pointer definition |
|||
*/ |
|||
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ |
|||
|
|||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup CAN_Error_Code CAN Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ |
|||
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ |
|||
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ |
|||
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ |
|||
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ |
|||
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ |
|||
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ |
|||
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ |
|||
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ |
|||
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ |
|||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ |
|||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ |
|||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ |
|||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ |
|||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ |
|||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ |
|||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ |
|||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ |
|||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ |
|||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ |
|||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ |
|||
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ |
|||
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ |
|||
|
|||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 |
|||
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ |
|||
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_InitStatus CAN InitStatus
|
|||
* @{ |
|||
*/ |
|||
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ |
|||
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_operating_mode CAN Operating Mode
|
|||
* @{ |
|||
*/ |
|||
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ |
|||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ |
|||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ |
|||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with |
|||
silent mode */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
|
|||
* @{ |
|||
*/ |
|||
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ |
|||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ |
|||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ |
|||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
|
|||
* @{ |
|||
*/ |
|||
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ |
|||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ |
|||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ |
|||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ |
|||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ |
|||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ |
|||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ |
|||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ |
|||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ |
|||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ |
|||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ |
|||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ |
|||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ |
|||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ |
|||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ |
|||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
|
|||
* @{ |
|||
*/ |
|||
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ |
|||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ |
|||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ |
|||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ |
|||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ |
|||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ |
|||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ |
|||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
|||
* @{ |
|||
*/ |
|||
#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ |
|||
#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
|||
* @{ |
|||
*/ |
|||
#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ |
|||
#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_filter_activation CAN Filter Activation
|
|||
* @{ |
|||
*/ |
|||
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ |
|||
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
|||
* @{ |
|||
*/ |
|||
#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ |
|||
#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_identifier_type CAN Identifier Type
|
|||
* @{ |
|||
*/ |
|||
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ |
|||
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
|||
* @{ |
|||
*/ |
|||
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ |
|||
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
|
|||
* @{ |
|||
*/ |
|||
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ |
|||
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
|
|||
* @{ |
|||
*/ |
|||
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ |
|||
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ |
|||
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CAN_flags CAN Flags
|
|||
* @{ |
|||
*/ |
|||
/* Transmit Flags */ |
|||
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ |
|||
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ |
|||
#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ |
|||
#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ |
|||
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ |
|||
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ |
|||
#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ |
|||
#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ |
|||
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ |
|||
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ |
|||
#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ |
|||
#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ |
|||
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ |
|||
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ |
|||
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ |
|||
#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ |
|||
#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ |
|||
#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ |
|||
|
|||
/* Receive Flags */ |
|||
#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ |
|||
#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ |
|||
#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ |
|||
#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ |
|||
|
|||
/* Operating Mode Flags */ |
|||
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ |
|||
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ |
|||
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ |
|||
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ |
|||
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ |
|||
|
|||
/* Error Flags */ |
|||
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ |
|||
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ |
|||
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup CAN_Interrupts CAN Interrupts
|
|||
* @{ |
|||
*/ |
|||
/* Transmit Interrupt */ |
|||
#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ |
|||
|
|||
/* Receive Interrupts */ |
|||
#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ |
|||
#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ |
|||
#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ |
|||
#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ |
|||
#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ |
|||
#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ |
|||
|
|||
/* Operating Mode Interrupts */ |
|||
#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ |
|||
#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ |
|||
|
|||
/* Error Interrupts */ |
|||
#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ |
|||
#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ |
|||
#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ |
|||
#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ |
|||
#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset CAN handle state
|
|||
* @param __HANDLE__ CAN handle. |
|||
* @retval None |
|||
*/ |
|||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 |
|||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) |
|||
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable the specified CAN interrupts. |
|||
* @param __HANDLE__ CAN handle. |
|||
* @param __INTERRUPT__ CAN Interrupt sources to enable. |
|||
* This parameter can be any combination of @arg CAN_Interrupts |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the specified CAN interrupts. |
|||
* @param __HANDLE__ CAN handle. |
|||
* @param __INTERRUPT__ CAN Interrupt sources to disable. |
|||
* This parameter can be any combination of @arg CAN_Interrupts |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
|||
|
|||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the CAN Handle. |
|||
* @param __INTERRUPT__ specifies the CAN interrupt source to check. |
|||
* This parameter can be a value of @arg CAN_Interrupts |
|||
* @retval The state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) |
|||
|
|||
/** @brief Check whether the specified CAN flag is set or not.
|
|||
* @param __HANDLE__ specifies the CAN Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of @arg CAN_flags |
|||
* @retval The state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ |
|||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) |
|||
|
|||
/** @brief Clear the specified CAN pending flag.
|
|||
* @param __HANDLE__ specifies the CAN Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag |
|||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag |
|||
* @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag |
|||
* @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag |
|||
* @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag |
|||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag |
|||
* @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag |
|||
* @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag |
|||
* @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag |
|||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag |
|||
* @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag |
|||
* @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag |
|||
* @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag |
|||
* @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag |
|||
* @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag |
|||
* @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag |
|||
* @arg CAN_FLAG_WKUI: Wake up Interrupt Flag |
|||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
|||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
|||
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @brief Initialization and Configuration functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization and de-initialization functions *****************************/ |
|||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); |
|||
|
|||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, |
|||
void (* pCallback)(CAN_HandleTypeDef *_hcan)); |
|||
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); |
|||
|
|||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
|
|||
* @brief Configuration functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Configuration functions ****************************************************/ |
|||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group3 Control functions
|
|||
* @brief Control functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Control functions **********************************************************/ |
|||
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); |
|||
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, |
|||
const uint8_t aData[], uint32_t *pTxMailbox); |
|||
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); |
|||
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); |
|||
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); |
|||
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); |
|||
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, |
|||
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); |
|||
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
|
|||
* @brief Interrupts management |
|||
* @{ |
|||
*/ |
|||
/* Interrupts management ******************************************************/ |
|||
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); |
|||
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); |
|||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
|
|||
* @brief Callback functions |
|||
* @{ |
|||
*/ |
|||
/* Callbacks functions ********************************************************/ |
|||
|
|||
void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); |
|||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
|
|||
* @brief CAN Peripheral State functions |
|||
* @{ |
|||
*/ |
|||
/* Peripheral State and Error functions ***************************************/ |
|||
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); |
|||
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); |
|||
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Types CAN Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define CAN_FLAG_MASK (0x000000FFU) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private Macros -----------------------------------------------------------*/ |
|||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ |
|||
((MODE) == CAN_MODE_LOOPBACK)|| \ |
|||
((MODE) == CAN_MODE_SILENT) || \ |
|||
((MODE) == CAN_MODE_SILENT_LOOPBACK)) |
|||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ |
|||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) |
|||
#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ |
|||
((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ |
|||
((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ |
|||
((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ |
|||
((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ |
|||
((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ |
|||
((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ |
|||
((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) |
|||
#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ |
|||
((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ |
|||
((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ |
|||
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) |
|||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) |
|||
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) |
|||
#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) |
|||
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) |
|||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ |
|||
((MODE) == CAN_FILTERMODE_IDLIST)) |
|||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ |
|||
((SCALE) == CAN_FILTERSCALE_32BIT)) |
|||
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ |
|||
((ACTIVATION) == CAN_FILTER_ENABLE)) |
|||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ |
|||
((FIFO) == CAN_FILTER_FIFO1)) |
|||
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ |
|||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ |
|||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) |
|||
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ |
|||
CAN_TX_MAILBOX2)) |
|||
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) |
|||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) |
|||
#define IS_CAN_DLC(DLC) ((DLC) <= 8U) |
|||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ |
|||
((IDTYPE) == CAN_ID_EXT)) |
|||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) |
|||
#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) |
|||
#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ |
|||
CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ |
|||
CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ |
|||
CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ |
|||
CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ |
|||
CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ |
|||
CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* End of private macros -----------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
#endif /* CAN1 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_CAN_H */ |
|||
@ -0,0 +1,792 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_cec.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of CEC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_CEC_H |
|||
#define STM32F4xx_HAL_CEC_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
#if defined (CEC) |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CEC
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief CEC Init Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
|||
It can be one of @ref CEC_Signal_Free_Time |
|||
and belongs to the set {0,...,7} where |
|||
0x0 is the default configuration |
|||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ |
|||
|
|||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
|||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE |
|||
or CEC_EXTENDED_TOLERANCE */ |
|||
|
|||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
|||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped. |
|||
CEC_RX_STOP_ON_BRE: reception is stopped. */ |
|||
|
|||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
|||
CEC line upon Bit Rising Error detection. |
|||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. |
|||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ |
|||
|
|||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
|||
CEC line upon Long Bit Period Error detection. |
|||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. |
|||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ |
|||
|
|||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
|||
upon an error detected on a broadcast message. |
|||
|
|||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: |
|||
|
|||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. |
|||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE |
|||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. |
|||
b) LBPE detection: error-bit generation on the CEC line |
|||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. |
|||
|
|||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. |
|||
no error-bit generation in case neither a) nor b) are satisfied. Additionally, |
|||
there is no error-bit generation in case of Short Bit Period Error detection in |
|||
a broadcast message while LSTN bit is set. */ |
|||
|
|||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
|||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. |
|||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ |
|||
|
|||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
|||
|
|||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its |
|||
own address (OAR). Messages addressed to different destination are ignored. |
|||
Broadcast messages are always received. |
|||
|
|||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own |
|||
address (OAR) with positive acknowledge. Messages addressed to different destination |
|||
are received, but without interfering with the CEC bus: no acknowledge sent. */ |
|||
|
|||
uint16_t OwnAddress; /*!< Own addresses configuration
|
|||
This parameter can be a value of @ref CEC_OWN_ADDRESS */ |
|||
|
|||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ |
|||
|
|||
|
|||
} CEC_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL CEC State definition |
|||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition). |
|||
* - gState contains CEC state information related to global Handle management |
|||
* and also information related to Tx operations. |
|||
* gState value coding follow below described bitmap : |
|||
* b7 (not used) |
|||
* x : Should be set to 0 |
|||
* b6 Error information |
|||
* 0 : No Error |
|||
* 1 : Error |
|||
* b5 CEC peripheral initialization status |
|||
* 0 : Reset (peripheral not initialized) |
|||
* 1 : Init done (peripheral initialized. HAL CEC Init function already called) |
|||
* b4-b3 (not used) |
|||
* xx : Should be set to 00 |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (peripheral busy with some configuration or internal operations) |
|||
* b1 (not used) |
|||
* x : Should be set to 0 |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* - RxState contains information related to Rx operations. |
|||
* RxState value coding follow below described bitmap : |
|||
* b7-b6 (not used) |
|||
* xx : Should be set to 00 |
|||
* b5 CEC peripheral initialization status |
|||
* 0 : Reset (peripheral not initialized) |
|||
* 1 : Init done (peripheral initialized) |
|||
* b4-b2 (not used) |
|||
* xxx : Should be set to 000 |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 (not used) |
|||
* x : Should be set to 0. |
|||
*/ |
|||
typedef uint32_t HAL_CEC_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief CEC handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) |
|||
typedef struct __CEC_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ |
|||
{ |
|||
CEC_TypeDef *Instance; /*!< CEC registers base address */ |
|||
|
|||
CEC_InitTypeDef Init; /*!< CEC communication parameters */ |
|||
|
|||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ |
|||
|
|||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ |
|||
|
|||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
|||
and also related to Tx operations. |
|||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */ |
|||
|
|||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
|||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */ |
|||
|
|||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
|||
in case error is reported */ |
|||
|
|||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) |
|||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef |
|||
*hcec); /*!< CEC Tx Transfer completed callback */ |
|||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, |
|||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ |
|||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ |
|||
|
|||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ |
|||
|
|||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ |
|||
} CEC_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL CEC Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ |
|||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ |
|||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ |
|||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ |
|||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ |
|||
} HAL_CEC_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL CEC Callback pointer definition |
|||
*/ |
|||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ |
|||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, |
|||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ |
|||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
/** @defgroup CEC_State_Definition CEC State Code Definition
|
|||
* @{ |
|||
*/ |
|||
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized |
|||
Value is allowed for gState and RxState */ |
|||
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use |
|||
Value is allowed for gState and RxState */ |
|||
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing |
|||
Value is allowed for gState only */ |
|||
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing |
|||
Value is allowed for RxState only */ |
|||
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing |
|||
Value is allowed for gState only */ |
|||
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing |
|||
Value is allowed for gState only */ |
|||
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
/** @defgroup CEC_Error_Code CEC Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ |
|||
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ |
|||
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ |
|||
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ |
|||
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ |
|||
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ |
|||
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ |
|||
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ |
|||
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ |
|||
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ |
|||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) |
|||
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */ |
|||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
|
|||
* @{ |
|||
*/ |
|||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) |
|||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) |
|||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) |
|||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) |
|||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) |
|||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) |
|||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) |
|||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
|
|||
* @{ |
|||
*/ |
|||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) |
|||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
|
|||
* @{ |
|||
*/ |
|||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) |
|||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
|
|||
* @{ |
|||
*/ |
|||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) |
|||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
|
|||
* @{ |
|||
*/ |
|||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) |
|||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
|
|||
* @{ |
|||
*/ |
|||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) |
|||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
|
|||
* @{ |
|||
*/ |
|||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) |
|||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_Listening_Mode CEC Listening mode option
|
|||
* @{ |
|||
*/ |
|||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) |
|||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
|
|||
* @{ |
|||
*/ |
|||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
|||
* @{ |
|||
*/ |
|||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
|||
* @{ |
|||
*/ |
|||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ |
|||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ |
|||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ |
|||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ |
|||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ |
|||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ |
|||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ |
|||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ |
|||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ |
|||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ |
|||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ |
|||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ |
|||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ |
|||
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ |
|||
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ |
|||
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
|
|||
* @{ |
|||
*/ |
|||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE |
|||
#define CEC_IT_TXERR CEC_IER_TXERRIE |
|||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE |
|||
#define CEC_IT_TXEND CEC_IER_TXENDIE |
|||
#define CEC_IT_TXBR CEC_IER_TXBRIE |
|||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE |
|||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE |
|||
#define CEC_IT_LBPE CEC_IER_LBPEIE |
|||
#define CEC_IT_SBPE CEC_IER_SBPEIE |
|||
#define CEC_IT_BRE CEC_IER_BREIE |
|||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE |
|||
#define CEC_IT_RXEND CEC_IER_RXENDIE |
|||
#define CEC_IT_RXBR CEC_IER_RXBRIE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_Flags_Definitions CEC Flags definition
|
|||
* @{ |
|||
*/ |
|||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE |
|||
#define CEC_FLAG_TXERR CEC_ISR_TXERR |
|||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR |
|||
#define CEC_FLAG_TXEND CEC_ISR_TXEND |
|||
#define CEC_FLAG_TXBR CEC_ISR_TXBR |
|||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST |
|||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE |
|||
#define CEC_FLAG_LBPE CEC_ISR_LBPE |
|||
#define CEC_FLAG_SBPE CEC_ISR_SBPE |
|||
#define CEC_FLAG_BRE CEC_ISR_BRE |
|||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR |
|||
#define CEC_FLAG_RXEND CEC_ISR_RXEND |
|||
#define CEC_FLAG_RXBR CEC_ISR_RXBR |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
|||
* @{ |
|||
*/ |
|||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ |
|||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
|||
* @{ |
|||
*/ |
|||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
|||
* @{ |
|||
*/ |
|||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset CEC handle gstate & RxState
|
|||
* @param __HANDLE__ CEC handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ |
|||
} while(0) |
|||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ |
|||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error |
|||
* @arg CEC_FLAG_TXERR: Tx Error. |
|||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. |
|||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). |
|||
* @arg CEC_FLAG_TXBR: Tx-Byte Request. |
|||
* @arg CEC_FLAG_ARBLST: Arbitration Lost |
|||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge |
|||
* @arg CEC_FLAG_LBPE: Rx Long period Error |
|||
* @arg CEC_FLAG_SBPE: Rx Short period Error |
|||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error |
|||
* @arg CEC_FLAG_RXOVR: Rx Overrun. |
|||
* @arg CEC_FLAG_RXEND: End Of Reception. |
|||
* @arg CEC_FLAG_RXBR: Rx-Byte Received. |
|||
* @retval ITStatus |
|||
*/ |
|||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
|||
|
|||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @param __FLAG__ specifies the interrupt/status flag to clear. |
|||
* This parameter can be one of the following values: |
|||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error |
|||
* @arg CEC_FLAG_TXERR: Tx Error. |
|||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. |
|||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). |
|||
* @arg CEC_FLAG_TXBR: Tx-Byte Request. |
|||
* @arg CEC_FLAG_ARBLST: Arbitration Lost |
|||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge |
|||
* @arg CEC_FLAG_LBPE: Rx Long period Error |
|||
* @arg CEC_FLAG_SBPE: Rx Short period Error |
|||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error |
|||
* @arg CEC_FLAG_RXOVR: Rx Overrun. |
|||
* @arg CEC_FLAG_RXEND: End Of Reception. |
|||
* @arg CEC_FLAG_RXBR: Rx-Byte Received. |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) |
|||
|
|||
/** @brief Enables the specified CEC interrupt.
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @param __INTERRUPT__ specifies the CEC interrupt to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable |
|||
* @arg CEC_IT_TXERR: Tx Error IT Enable |
|||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable |
|||
* @arg CEC_IT_TXEND: End of transmission IT Enable |
|||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable |
|||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable |
|||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable |
|||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable |
|||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable |
|||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable |
|||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable |
|||
* @arg CEC_IT_RXEND: End Of Reception IT Enable |
|||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
|||
|
|||
/** @brief Disables the specified CEC interrupt.
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @param __INTERRUPT__ specifies the CEC interrupt to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable |
|||
* @arg CEC_IT_TXERR: Tx Error IT Enable |
|||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable |
|||
* @arg CEC_IT_TXEND: End of transmission IT Enable |
|||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable |
|||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable |
|||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable |
|||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable |
|||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable |
|||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable |
|||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable |
|||
* @arg CEC_IT_RXEND: End Of Reception IT Enable |
|||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) |
|||
|
|||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @param __INTERRUPT__ specifies the CEC interrupt to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable |
|||
* @arg CEC_IT_TXERR: Tx Error IT Enable |
|||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable |
|||
* @arg CEC_IT_TXEND: End of transmission IT Enable |
|||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable |
|||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable |
|||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable |
|||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable |
|||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable |
|||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable |
|||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable |
|||
* @arg CEC_IT_RXEND: End Of Reception IT Enable |
|||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable |
|||
* @retval FlagStatus |
|||
*/ |
|||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) |
|||
|
|||
/** @brief Enables the CEC device
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) |
|||
|
|||
/** @brief Disables the CEC device
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) |
|||
|
|||
/** @brief Set Transmission Start flag
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) |
|||
|
|||
/** @brief Set Transmission End flag
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval none |
|||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. |
|||
*/ |
|||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) |
|||
|
|||
/** @brief Get Transmission Start flag
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval FlagStatus |
|||
*/ |
|||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) |
|||
|
|||
/** @brief Get Transmission End flag
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval FlagStatus |
|||
*/ |
|||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) |
|||
|
|||
/** @brief Clear OAR register
|
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) |
|||
|
|||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
|||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand |
|||
* @param __HANDLE__ specifies the CEC Handle. |
|||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) |
|||
* @retval none |
|||
*/ |
|||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup CEC_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CEC_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions ****************************/ |
|||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); |
|||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); |
|||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); |
|||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); |
|||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); |
|||
|
|||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, |
|||
pCEC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); |
|||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CEC_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ***************************************************/ |
|||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, |
|||
const uint8_t *pData, uint32_t Size); |
|||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); |
|||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); |
|||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); |
|||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); |
|||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); |
|||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CEC_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ************************************************/ |
|||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); |
|||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup CEC_Private_Types CEC Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) |
|||
|
|||
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ |
|||
((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) |
|||
|
|||
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ |
|||
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) |
|||
|
|||
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ |
|||
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) |
|||
|
|||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ |
|||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) |
|||
|
|||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ |
|||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) |
|||
|
|||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ |
|||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) |
|||
|
|||
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ |
|||
((__MODE__) == CEC_FULL_LISTENING_MODE)) |
|||
|
|||
/** @brief Check CEC message size.
|
|||
* The message size is the payload size: without counting the header, |
|||
* it varies from 0 byte (ping operation, one header only, no payload) to |
|||
* 15 bytes (1 opcode and up to 14 operands following the header). |
|||
* @param __SIZE__ CEC message size. |
|||
* @retval Test result (TRUE or FALSE). |
|||
*/ |
|||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) |
|||
|
|||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
|||
* OAR address is written in a 15-bit field within CEC_CFGR register. |
|||
* @param __ADDRESS__ CEC own address. |
|||
* @retval Test result (TRUE or FALSE). |
|||
*/ |
|||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) |
|||
|
|||
/** @brief Check CEC initiator or destination logical address setting.
|
|||
* Initiator and destination addresses are coded over 4 bits. |
|||
* @param __ADDRESS__ CEC initiator or logical address. |
|||
* @retval Test result (TRUE or FALSE). |
|||
*/ |
|||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* CEC */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xxHAL_CEC_H */ |
|||
|
|||
@ -0,0 +1,500 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_conf_template.h |
|||
* @author MCD Application Team |
|||
* @brief HAL configuration template file. |
|||
* This file should be copied to the application folder and renamed |
|||
* to stm32f4xx_hal_conf.h. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_CONF_H |
|||
#define __STM32F4xx_HAL_CONF_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/* ########################## Module Selection ############################## */ |
|||
/**
|
|||
* @brief This is the list of modules to be used in the HAL driver |
|||
*/ |
|||
#define HAL_MODULE_ENABLED |
|||
#define HAL_ADC_MODULE_ENABLED |
|||
#define HAL_CAN_MODULE_ENABLED |
|||
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ |
|||
#define HAL_CRC_MODULE_ENABLED |
|||
#define HAL_CEC_MODULE_ENABLED |
|||
#define HAL_CRYP_MODULE_ENABLED |
|||
#define HAL_DAC_MODULE_ENABLED |
|||
#define HAL_DCMI_MODULE_ENABLED |
|||
#define HAL_DMA_MODULE_ENABLED |
|||
#define HAL_DMA2D_MODULE_ENABLED |
|||
#define HAL_ETH_MODULE_ENABLED |
|||
#define HAL_FLASH_MODULE_ENABLED |
|||
#define HAL_NAND_MODULE_ENABLED |
|||
#define HAL_NOR_MODULE_ENABLED |
|||
#define HAL_PCCARD_MODULE_ENABLED |
|||
#define HAL_SRAM_MODULE_ENABLED |
|||
#define HAL_SDRAM_MODULE_ENABLED |
|||
#define HAL_HASH_MODULE_ENABLED |
|||
#define HAL_GPIO_MODULE_ENABLED |
|||
#define HAL_EXTI_MODULE_ENABLED |
|||
#define HAL_I2C_MODULE_ENABLED |
|||
#define HAL_SMBUS_MODULE_ENABLED |
|||
#define HAL_I2S_MODULE_ENABLED |
|||
#define HAL_IWDG_MODULE_ENABLED |
|||
#define HAL_LTDC_MODULE_ENABLED |
|||
#define HAL_DSI_MODULE_ENABLED |
|||
#define HAL_PWR_MODULE_ENABLED |
|||
#define HAL_QSPI_MODULE_ENABLED |
|||
#define HAL_RCC_MODULE_ENABLED |
|||
#define HAL_RNG_MODULE_ENABLED |
|||
#define HAL_RTC_MODULE_ENABLED |
|||
#define HAL_SAI_MODULE_ENABLED |
|||
#define HAL_SD_MODULE_ENABLED |
|||
#define HAL_SPI_MODULE_ENABLED |
|||
#define HAL_TIM_MODULE_ENABLED |
|||
#define HAL_UART_MODULE_ENABLED |
|||
#define HAL_USART_MODULE_ENABLED |
|||
#define HAL_IRDA_MODULE_ENABLED |
|||
#define HAL_SMARTCARD_MODULE_ENABLED |
|||
#define HAL_WWDG_MODULE_ENABLED |
|||
#define HAL_CORTEX_MODULE_ENABLED |
|||
#define HAL_PCD_MODULE_ENABLED |
|||
#define HAL_HCD_MODULE_ENABLED |
|||
#define HAL_FMPI2C_MODULE_ENABLED |
|||
#define HAL_FMPSMBUS_MODULE_ENABLED |
|||
#define HAL_SPDIFRX_MODULE_ENABLED |
|||
#define HAL_DFSDM_MODULE_ENABLED |
|||
#define HAL_LPTIM_MODULE_ENABLED |
|||
#define HAL_MMC_MODULE_ENABLED |
|||
|
|||
/* ########################## HSE/HSI Values adaptation ##################### */ |
|||
/**
|
|||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. |
|||
* This value is used by the RCC HAL module to compute the system frequency |
|||
* (when HSE is used as system clock source, directly or through the PLL). |
|||
*/ |
|||
#if !defined (HSE_VALUE) |
|||
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ |
|||
#endif /* HSE_VALUE */ |
|||
|
|||
#if !defined (HSE_STARTUP_TIMEOUT) |
|||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ |
|||
#endif /* HSE_STARTUP_TIMEOUT */ |
|||
|
|||
/**
|
|||
* @brief Internal High Speed oscillator (HSI) value. |
|||
* This value is used by the RCC HAL module to compute the system frequency |
|||
* (when HSI is used as system clock source, directly or through the PLL). |
|||
*/ |
|||
#if !defined (HSI_VALUE) |
|||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */ |
|||
#endif /* HSI_VALUE */ |
|||
|
|||
/**
|
|||
* @brief Internal Low Speed oscillator (LSI) value. |
|||
*/ |
|||
#if !defined (LSI_VALUE) |
|||
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ |
|||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
|||
The real value may vary depending on the variations |
|||
in voltage and temperature. */ |
|||
/**
|
|||
* @brief External Low Speed oscillator (LSE) value. |
|||
*/ |
|||
#if !defined (LSE_VALUE) |
|||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ |
|||
#endif /* LSE_VALUE */ |
|||
|
|||
#if !defined (LSE_STARTUP_TIMEOUT) |
|||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ |
|||
#endif /* LSE_STARTUP_TIMEOUT */ |
|||
|
|||
/**
|
|||
* @brief External clock source for I2S peripheral |
|||
* This value is used by the I2S HAL module to compute the I2S clock source |
|||
* frequency, this source is inserted directly through I2S_CKIN pad. |
|||
*/ |
|||
#if !defined (EXTERNAL_CLOCK_VALUE) |
|||
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/ |
|||
#endif /* EXTERNAL_CLOCK_VALUE */ |
|||
|
|||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
|||
=== you can define the HSE value in your toolchain compiler preprocessor. */ |
|||
|
|||
/* ########################### System Configuration ######################### */ |
|||
/**
|
|||
* @brief This is the HAL system configuration section |
|||
*/ |
|||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */ |
|||
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ |
|||
#define USE_RTOS 0U |
|||
#define PREFETCH_ENABLE 1U |
|||
#define INSTRUCTION_CACHE_ENABLE 1U |
|||
#define DATA_CACHE_ENABLE 1U |
|||
|
|||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ |
|||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ |
|||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ |
|||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ |
|||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ |
|||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ |
|||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ |
|||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ |
|||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ |
|||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ |
|||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ |
|||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ |
|||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ |
|||
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ |
|||
#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ |
|||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ |
|||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ |
|||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ |
|||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ |
|||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ |
|||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ |
|||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ |
|||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ |
|||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ |
|||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ |
|||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ |
|||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ |
|||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ |
|||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ |
|||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ |
|||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ |
|||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ |
|||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ |
|||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ |
|||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ |
|||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ |
|||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ |
|||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ |
|||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ |
|||
|
|||
/* ########################## Assert Selection ############################## */ |
|||
/**
|
|||
* @brief Uncomment the line below to expanse the "assert_param" macro in the |
|||
* HAL drivers code |
|||
*/ |
|||
/* #define USE_FULL_ASSERT 1U */ |
|||
|
|||
/* ################## Ethernet peripheral configuration ##################### */ |
|||
|
|||
/* Section 1 : Ethernet peripheral configuration */ |
|||
|
|||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ |
|||
#define MAC_ADDR0 2U |
|||
#define MAC_ADDR1 0U |
|||
#define MAC_ADDR2 0U |
|||
#define MAC_ADDR3 0U |
|||
#define MAC_ADDR4 0U |
|||
#define MAC_ADDR5 0U |
|||
|
|||
/* Definition of the Ethernet driver buffers size and count */ |
|||
#define ETH_RX_BUF_SIZE 1528U /* ETH Max buffer size for receive */ |
|||
#define ETH_TX_BUF_SIZE 1528U /* ETH Max buffer size for transmit */ |
|||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
|||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
|||
|
|||
/* Section 2: PHY configuration section */ |
|||
|
|||
/* DP83848 PHY Address*/ |
|||
#define DP83848_PHY_ADDRESS 0x01U |
|||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
|||
#define PHY_RESET_DELAY 0x000000FFU |
|||
/* PHY Configuration delay */ |
|||
#define PHY_CONFIG_DELAY 0x00000FFFU |
|||
|
|||
#define PHY_READ_TO 0x0000FFFFU |
|||
#define PHY_WRITE_TO 0x0000FFFFU |
|||
|
|||
/* Section 3: Common PHY Registers */ |
|||
|
|||
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ |
|||
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ |
|||
|
|||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ |
|||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ |
|||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ |
|||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ |
|||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ |
|||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ |
|||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ |
|||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ |
|||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ |
|||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ |
|||
|
|||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ |
|||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ |
|||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ |
|||
|
|||
/* Section 4: Extended PHY Registers */ |
|||
|
|||
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ |
|||
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ |
|||
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ |
|||
|
|||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ |
|||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ |
|||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ |
|||
|
|||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ |
|||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ |
|||
|
|||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ |
|||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ |
|||
|
|||
/* ################## SPI peripheral configuration ########################## */ |
|||
|
|||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
|||
* Activated: CRC code is present inside driver |
|||
* Deactivated: CRC code cleaned from driver |
|||
*/ |
|||
|
|||
#define USE_SPI_CRC 1U |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
/**
|
|||
* @brief Include module's header file |
|||
*/ |
|||
|
|||
#ifdef HAL_RCC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_rcc.h" |
|||
#endif /* HAL_RCC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_GPIO_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_gpio.h" |
|||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_EXTI_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_exti.h" |
|||
#endif /* HAL_EXTI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DMA_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_dma.h" |
|||
#endif /* HAL_DMA_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_CORTEX_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_cortex.h" |
|||
#endif /* HAL_CORTEX_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_ADC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_adc.h" |
|||
#endif /* HAL_ADC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_CAN_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_can.h" |
|||
#endif /* HAL_CAN_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_can_legacy.h" |
|||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_CRC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_crc.h" |
|||
#endif /* HAL_CRC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_CRYP_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_cryp.h" |
|||
#endif /* HAL_CRYP_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DMA2D_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_dma2d.h" |
|||
#endif /* HAL_DMA2D_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DAC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_dac.h" |
|||
#endif /* HAL_DAC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DCMI_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_dcmi.h" |
|||
#endif /* HAL_DCMI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_ETH_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_eth.h" |
|||
#endif /* HAL_ETH_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_FLASH_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_flash.h" |
|||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SRAM_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_sram.h" |
|||
#endif /* HAL_SRAM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_NOR_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_nor.h" |
|||
#endif /* HAL_NOR_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_NAND_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_nand.h" |
|||
#endif /* HAL_NAND_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_PCCARD_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_pccard.h" |
|||
#endif /* HAL_PCCARD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SDRAM_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_sdram.h" |
|||
#endif /* HAL_SDRAM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_HASH_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_hash.h" |
|||
#endif /* HAL_HASH_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_I2C_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_i2c.h" |
|||
#endif /* HAL_I2C_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SMBUS_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_smbus.h" |
|||
#endif /* HAL_SMBUS_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_I2S_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_i2s.h" |
|||
#endif /* HAL_I2S_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_IWDG_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_iwdg.h" |
|||
#endif /* HAL_IWDG_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_LTDC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_ltdc.h" |
|||
#endif /* HAL_LTDC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_PWR_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_pwr.h" |
|||
#endif /* HAL_PWR_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_RNG_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_rng.h" |
|||
#endif /* HAL_RNG_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_RTC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_rtc.h" |
|||
#endif /* HAL_RTC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SAI_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_sai.h" |
|||
#endif /* HAL_SAI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SD_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_sd.h" |
|||
#endif /* HAL_SD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SPI_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_spi.h" |
|||
#endif /* HAL_SPI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_TIM_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_tim.h" |
|||
#endif /* HAL_TIM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_UART_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_uart.h" |
|||
#endif /* HAL_UART_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_USART_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_usart.h" |
|||
#endif /* HAL_USART_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_IRDA_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_irda.h" |
|||
#endif /* HAL_IRDA_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SMARTCARD_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_smartcard.h" |
|||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_WWDG_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_wwdg.h" |
|||
#endif /* HAL_WWDG_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_PCD_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_pcd.h" |
|||
#endif /* HAL_PCD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_HCD_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_hcd.h" |
|||
#endif /* HAL_HCD_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DSI_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_dsi.h" |
|||
#endif /* HAL_DSI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_QSPI_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_qspi.h" |
|||
#endif /* HAL_QSPI_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_CEC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_cec.h" |
|||
#endif /* HAL_CEC_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_FMPI2C_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_fmpi2c.h" |
|||
#endif /* HAL_FMPI2C_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_FMPSMBUS_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_fmpsmbus.h" |
|||
#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_SPDIFRX_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_spdifrx.h" |
|||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_DFSDM_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_dfsdm.h" |
|||
#endif /* HAL_DFSDM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_LPTIM_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_lptim.h" |
|||
#endif /* HAL_LPTIM_MODULE_ENABLED */ |
|||
|
|||
#ifdef HAL_MMC_MODULE_ENABLED |
|||
#include "stm32f4xx_hal_mmc.h" |
|||
#endif /* HAL_MMC_MODULE_ENABLED */ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
#ifdef USE_FULL_ASSERT |
|||
/**
|
|||
* @brief The assert_param macro is used for function's parameters check. |
|||
* @param expr If expr is false, it calls assert_failed function |
|||
* which reports the name of the source file and the source |
|||
* line number of the call that failed. |
|||
* If expr is true, it returns no value. |
|||
* @retval None |
|||
*/ |
|||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
|||
/* Exported functions ------------------------------------------------------- */ |
|||
void assert_failed(uint8_t* file, uint32_t line); |
|||
#else |
|||
#define assert_param(expr) ((void)0U) |
|||
#endif /* USE_FULL_ASSERT */ |
|||
|
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_CONF_H */ |
|||
|
|||
|
|||
|
|||
@ -0,0 +1,181 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_crc.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of CRC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_CRC_H |
|||
#define STM32F4xx_HAL_CRC_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CRC
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief CRC HAL State Structure definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ |
|||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ |
|||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ |
|||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ |
|||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ |
|||
} HAL_CRC_StateTypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @brief CRC Handle Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
CRC_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< CRC Locking object */ |
|||
|
|||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ |
|||
|
|||
} CRC_HandleTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset CRC handle state.
|
|||
* @param __HANDLE__ CRC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) |
|||
|
|||
/**
|
|||
* @brief Reset CRC Data Register. |
|||
* @param __HANDLE__ CRC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) |
|||
|
|||
/**
|
|||
* @brief Store data in the Independent Data (ID) register. |
|||
* @param __HANDLE__ CRC handle |
|||
* @param __VALUE__ Value to be stored in the ID register |
|||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) |
|||
|
|||
/**
|
|||
* @brief Return the data stored in the Independent Data (ID) register. |
|||
* @param __HANDLE__ CRC handle |
|||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits |
|||
* @retval Value of the ID register |
|||
*/ |
|||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Private macros --------------------------------------------------------*/ |
|||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization and de-initialization functions ****************************/ |
|||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); |
|||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); |
|||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); |
|||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Peripheral Control functions ***********************************************/ |
|||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); |
|||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Peripheral State and Error functions ***************************************/ |
|||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
|||
* @{ |
|||
*/ |
|||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_CRC_H */ |
|||
@ -0,0 +1,683 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_cryp.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of CRYP HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_CRYP_H |
|||
#define __STM32F4xx_HAL_CRYP_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (AES) || defined (CRYP) |
|||
/** @addtogroup CRYP
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief CRYP Init Structure definition |
|||
*/ |
|||
|
|||
typedef struct |
|||
{ |
|||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
|||
This parameter can be a value of @ref CRYP_Data_Type */ |
|||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
|||
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ |
|||
uint32_t *pKey; /*!< The key used for encryption/decryption */ |
|||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
|||
counter in CTR mode */ |
|||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
|||
AES Algorithm ECB/CBC/CTR/GCM or CCM |
|||
This parameter can be a value of @ref CRYP_Algorithm_Mode */ |
|||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
|||
GCM : also known as Additional Authentication Data |
|||
CCM : named B1 composed of the associated data length and Associated Data. */ |
|||
uint32_t HeaderSize; /*!< The size of header buffer in word */ |
|||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ |
|||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ |
|||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ |
|||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
|||
Vector only once and to skip configuration for consecutive processings. |
|||
This parameter can be a value of @ref CRYP_Configuration_Skip */ |
|||
|
|||
} CRYP_ConfigTypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @brief CRYP State Structure definition |
|||
*/ |
|||
|
|||
typedef enum |
|||
{ |
|||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ |
|||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ |
|||
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */ |
|||
} HAL_CRYP_STATETypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @brief CRYP handle Structure definition |
|||
*/ |
|||
|
|||
typedef struct __CRYP_HandleTypeDef |
|||
{ |
|||
#if defined (CRYP) |
|||
CRYP_TypeDef *Instance; /*!< CRYP registers base address */ |
|||
#else /* AES*/ |
|||
AES_TypeDef *Instance; /*!< AES Register base address */ |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ |
|||
|
|||
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
|
|||
This parameter can be a value of ENABLE/DISABLE */ |
|||
|
|||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ |
|||
|
|||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ |
|||
|
|||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */ |
|||
|
|||
__IO uint16_t CrypInCount; /*!< Counter of input data */ |
|||
|
|||
__IO uint16_t CrypOutCount; /*!< Counter of output data */ |
|||
|
|||
uint16_t Size; /*!< length of input data in word */ |
|||
|
|||
uint32_t Phase; /*!< CRYP peripheral phase */ |
|||
|
|||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< CRYP locking object */ |
|||
|
|||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ |
|||
|
|||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
|||
configuration can be skipped */ |
|||
|
|||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
|||
for a single signature computation after several |
|||
messages processing */ |
|||
|
|||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) |
|||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ |
|||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ |
|||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */ |
|||
|
|||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */ |
|||
|
|||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ |
|||
} CRYP_HandleTypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) |
|||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
|||
* @brief HAL CRYP Callback ID enumeration definition |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */ |
|||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */ |
|||
HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */ |
|||
|
|||
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */ |
|||
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */ |
|||
|
|||
} HAL_CRYP_CallbackIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
|||
* @brief HAL CRYP Callback pointer definition |
|||
* @{ |
|||
*/ |
|||
|
|||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
|||
* @{ |
|||
*/ |
|||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */ |
|||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */ |
|||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */ |
|||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */ |
|||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ |
|||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */ |
|||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */ |
|||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) |
|||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ |
|||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ |
|||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
|||
* @{ |
|||
*/ |
|||
#if defined(CRYP) |
|||
|
|||
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB |
|||
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC |
|||
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB |
|||
#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC |
|||
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB |
|||
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC |
|||
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR |
|||
#if defined (CRYP_CR_ALGOMODE_AES_GCM) |
|||
#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM |
|||
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM |
|||
#endif /* GCM CCM defined*/ |
|||
#else /* AES*/ |
|||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */ |
|||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ |
|||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ |
|||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */ |
|||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */ |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
|||
* @{ |
|||
*/ |
|||
#if defined(CRYP) |
|||
#define CRYP_KEYSIZE_128B 0x00000000U |
|||
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0 |
|||
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1 |
|||
#else /* AES*/ |
|||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */ |
|||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ |
|||
#endif /* End AES or CRYP */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
|||
* @{ |
|||
*/ |
|||
#if defined(CRYP) |
|||
#define CRYP_DATATYPE_32B 0x00000000U |
|||
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0 |
|||
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1 |
|||
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE |
|||
#else /* AES*/ |
|||
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */ |
|||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */ |
|||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */ |
|||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */ |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
|||
* @{ |
|||
*/ |
|||
#if defined (CRYP) |
|||
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */ |
|||
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */ |
|||
#else /* AES*/ |
|||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */ |
|||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */ |
|||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */ |
|||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */ |
|||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */ |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Flags CRYP Flags
|
|||
* @{ |
|||
*/ |
|||
#if defined (CRYP) |
|||
/* Flags in the SR register */ |
|||
#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */ |
|||
#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */ |
|||
#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */ |
|||
#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */ |
|||
#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data |
|||
or a key preparation (for AES decryption). */ |
|||
/* Flags in the RISR register */ |
|||
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */ |
|||
#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/ |
|||
#else /* AES*/ |
|||
/* status flags */ |
|||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */ |
|||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */ |
|||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */ |
|||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */ |
|||
/* clearing flags */ |
|||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */ |
|||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */ |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ |
|||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset CRYP handle state
|
|||
* @param __HANDLE__ specifies the CRYP handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\ |
|||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\ |
|||
(__HANDLE__)->MspInitCallback = NULL;\ |
|||
(__HANDLE__)->MspDeInitCallback = NULL;\ |
|||
}while(0) |
|||
#else |
|||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET) |
|||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable/Disable the CRYP peripheral. |
|||
* @param __HANDLE__: specifies the CRYP handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined(CRYP) |
|||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN) |
|||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN) |
|||
#else /* AES*/ |
|||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN) |
|||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN) |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/** @brief Check whether the specified CRYP status flag is set or not.
|
|||
* @param __FLAG__: specifies the flag to check. |
|||
* This parameter can be one of the following values for TinyAES: |
|||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden |
|||
* @arg @ref CRYP_IT_WRERR Write Error |
|||
* @arg @ref CRYP_IT_RDERR Read Error |
|||
* @arg @ref CRYP_IT_CCF Computation Complete |
|||
* This parameter can be one of the following values for CRYP: |
|||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data |
|||
* or a key preparation (for AES decryption). |
|||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty |
|||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full |
|||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending |
|||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty |
|||
* @arg CRYP_FLAG_OFFU: Output FIFO is full |
|||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending |
|||
* @retval The state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define CRYP_FLAG_MASK 0x0000001FU |
|||
#if defined(CRYP) |
|||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ |
|||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) |
|||
#else /* AES*/ |
|||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/** @brief Clear the CRYP pending status flag.
|
|||
* @param __FLAG__: specifies the flag to clear. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear |
|||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear |
|||
* @param __HANDLE__: specifies the CRYP handle. |
|||
* @retval None |
|||
*/ |
|||
|
|||
#if defined(AES) |
|||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__)) |
|||
|
|||
|
|||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
|||
* @param __INTERRUPT__: CRYP interrupt source to check |
|||
* This parameter can be one of the following values for TinyAES: |
|||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) |
|||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt |
|||
* @param __HANDLE__: specifies the CRYP handle. |
|||
* @retval State of interruption (TRUE or FALSE). |
|||
*/ |
|||
|
|||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
|
|||
#endif /* AES */ |
|||
|
|||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
|||
* @param __INTERRUPT__: specifies the interrupt to check. |
|||
* This parameter can be one of the following values for TinyAES: |
|||
* @arg @ref CRYP_IT_WRERR Write Error |
|||
* @arg @ref CRYP_IT_RDERR Read Error |
|||
* @arg @ref CRYP_IT_CCF Computation Complete |
|||
* This parameter can be one of the following values for CRYP: |
|||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status |
|||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status |
|||
* @param __HANDLE__: specifies the CRYP handle. |
|||
* @retval The state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#if defined(CRYP) |
|||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
#else /* AES*/ |
|||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @brief Enable the CRYP interrupt. |
|||
* @param __INTERRUPT__: CRYP Interrupt. |
|||
* This parameter can be one of the following values for TinyAES: |
|||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) |
|||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt |
|||
* This parameter can be one of the following values for CRYP: |
|||
* @ CRYP_IT_INI : Input FIFO service interrupt mask. |
|||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt. |
|||
* @param __HANDLE__: specifies the CRYP handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined(CRYP) |
|||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__)) |
|||
#else /* AES*/ |
|||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @brief Disable the CRYP interrupt. |
|||
* @param __INTERRUPT__: CRYP Interrupt. |
|||
* This parameter can be one of the following values for TinyAES: |
|||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) |
|||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt |
|||
* This parameter can be one of the following values for CRYP: |
|||
* @ CRYP_IT_INI : Input FIFO service interrupt mask. |
|||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt. |
|||
* @param __HANDLE__: specifies the CRYP handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined(CRYP) |
|||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__)) |
|||
#else /* AES*/ |
|||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES) |
|||
/* Include CRYP HAL Extended module */ |
|||
#include "stm32f4xx_hal_cryp_ex.h" |
|||
#endif /* AES or GCM CCM defined*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CRYP_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); |
|||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); |
|||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); |
|||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); |
|||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); |
|||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); |
|||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, |
|||
pCRYP_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup CRYP_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* encryption/decryption ***********************************/ |
|||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); |
|||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); |
|||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); |
|||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @addtogroup CRYP_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Interrupt Handler functions **********************************************/ |
|||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); |
|||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); |
|||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); |
|||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); |
|||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); |
|||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros --------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
|||
* @{ |
|||
*/ |
|||
#if defined(CRYP) |
|||
#if defined (CRYP_CR_ALGOMODE_AES_GCM) |
|||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \ |
|||
((ALGORITHM) == CRYP_DES_CBC) || \ |
|||
((ALGORITHM) == CRYP_TDES_ECB) || \ |
|||
((ALGORITHM) == CRYP_TDES_CBC) || \ |
|||
((ALGORITHM) == CRYP_AES_ECB) || \ |
|||
((ALGORITHM) == CRYP_AES_CBC) || \ |
|||
((ALGORITHM) == CRYP_AES_CTR) || \ |
|||
((ALGORITHM) == CRYP_AES_GCM) || \ |
|||
((ALGORITHM) == CRYP_AES_CCM)) |
|||
#else /*NO GCM CCM */ |
|||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \ |
|||
((ALGORITHM) == CRYP_DES_CBC) || \ |
|||
((ALGORITHM) == CRYP_TDES_ECB) || \ |
|||
((ALGORITHM) == CRYP_TDES_CBC) || \ |
|||
((ALGORITHM) == CRYP_AES_ECB) || \ |
|||
((ALGORITHM) == CRYP_AES_CBC) || \ |
|||
((ALGORITHM) == CRYP_AES_CTR)) |
|||
#endif /* GCM CCM defined*/ |
|||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ |
|||
((KEYSIZE) == CRYP_KEYSIZE_192B) || \ |
|||
((KEYSIZE) == CRYP_KEYSIZE_256B)) |
|||
#else /* AES*/ |
|||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ |
|||
((ALGORITHM) == CRYP_AES_CBC) || \ |
|||
((ALGORITHM) == CRYP_AES_CTR) || \ |
|||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ |
|||
((ALGORITHM) == CRYP_AES_CCM)) |
|||
|
|||
|
|||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ |
|||
((KEYSIZE) == CRYP_KEYSIZE_256B)) |
|||
#endif /* End AES or CRYP */ |
|||
|
|||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \ |
|||
((DATATYPE) == CRYP_DATATYPE_16B) || \ |
|||
((DATATYPE) == CRYP_DATATYPE_8B) || \ |
|||
((DATATYPE) == CRYP_DATATYPE_1B)) |
|||
|
|||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ |
|||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* TinyAES or CRYP*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_CRYP_H */ |
|||
|
|||
@ -0,0 +1,142 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_cryp_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of CRYP HAL Extension module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_CRYP_EX_H |
|||
#define __STM32F4xx_HAL_CRYP_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CRYPEx
|
|||
* @{ |
|||
*/ |
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
|||
* @{ |
|||
*/ |
|||
#if defined (CRYP) || defined (AES) |
|||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* CRYP||AES */ |
|||
|
|||
#if defined (AES) |
|||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); |
|||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* AES */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_CRYP_EX_H */ |
|||
|
|||
@ -0,0 +1,563 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_dcmi.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of DCMI HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file in |
|||
* the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_DCMI_H |
|||
#define __STM32F4xx_HAL_DCMI_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
|||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ |
|||
defined(STM32F479xx) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/* Include DCMI HAL Extended module */ |
|||
/* (include on top of file since DCMI structures are defined in extended file) */ |
|||
#include "stm32f4xx_hal_dcmi_ex.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup DCMI DCMI
|
|||
* @brief DCMI HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup DCMI_Exported_Types DCMI Exported Types
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief DCMI Embedded Synchronisation CODE Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */ |
|||
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */ |
|||
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */ |
|||
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */ |
|||
}DCMI_SyncUnmaskTypeDef; |
|||
/**
|
|||
* @brief HAL DCMI State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */ |
|||
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */ |
|||
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */ |
|||
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ |
|||
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ |
|||
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ |
|||
}HAL_DCMI_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief DCMI handle Structure definition |
|||
*/ |
|||
typedef struct __DCMI_HandleTypeDef |
|||
{ |
|||
DCMI_TypeDef *Instance; /*!< DCMI Register base address */ |
|||
|
|||
DCMI_InitTypeDef Init; /*!< DCMI parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< DCMI locking object */ |
|||
|
|||
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */ |
|||
|
|||
__IO uint32_t XferCount; /*!< DMA transfer counter */ |
|||
|
|||
__IO uint32_t XferSize; /*!< DMA transfer size */ |
|||
|
|||
uint32_t XferTransferNumber; /*!< DMA transfer number */ |
|||
|
|||
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */ |
|||
|
|||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< DCMI Error code */ |
|||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) |
|||
void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ |
|||
void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ |
|||
void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */ |
|||
void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */ |
|||
void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */ |
|||
void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */ |
|||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ |
|||
}DCMI_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) |
|||
typedef enum |
|||
{ |
|||
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */ |
|||
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */ |
|||
HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */ |
|||
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */ |
|||
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */ |
|||
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */ |
|||
|
|||
}HAL_DCMI_CallbackIDTypeDef; |
|||
|
|||
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); |
|||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Error_Code DCMI Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_DCMI_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_DCMI_ERROR_OVR 0x00000001U /*!< Overrun error */ |
|||
#define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */ |
|||
#define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
|||
#define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */ |
|||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) |
|||
#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */ |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_MODE_CONTINUOUS 0x00000000U /*!< The received data are transferred continuously |
|||
into the destination memory through the DMA */ |
|||
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of |
|||
frame and then transfers a single frame through the DMA */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_SYNCHRO_HARDWARE 0x00000000U /*!< Hardware synchronization data capture (frame/line start/stop) |
|||
is synchronized with the HSYNC/VSYNC signals */ |
|||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with |
|||
synchronization codes embedded in the data flow */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_PCKPOLARITY_FALLING 0x00000000U /*!< Pixel clock active on Falling edge */ |
|||
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_VSPOLARITY_LOW 0x00000000U /*!< Vertical synchronization active Low */ |
|||
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_HSPOLARITY_LOW 0x00000000U /*!< Horizontal synchronization active Low */ |
|||
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_JPEG_DISABLE 0x00000000U /*!< Mode JPEG Disabled */ |
|||
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_CR_ALL_FRAME 0x00000000U /*!< All frames are captured */ |
|||
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ |
|||
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_EXTEND_DATA_8B 0x00000000U /*!< Interface captures 8-bit data on every pixel clock */ |
|||
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ |
|||
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ |
|||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_WINDOW_COORDINATE 0x3FFFU /*!< Window coordinate */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Window_Height DCMI Window Height
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_WINDOW_HEIGHT 0x1FFFU /*!< Window Height */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */ |
|||
#define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */ |
|||
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */ |
|||
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */ |
|||
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */ |
|||
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMI_Flags DCMI Flags
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief DCMI SR register |
|||
*/ |
|||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */ |
|||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */ |
|||
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ |
|||
/**
|
|||
* @brief DCMI RIS register |
|||
*/ |
|||
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) /*!< Frame capture complete interrupt flag */ |
|||
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RISR_OVR_RIS) /*!< Overrun interrupt flag */ |
|||
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) /*!< Synchronization error interrupt flag */ |
|||
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) /*!< VSYNC interrupt flag */ |
|||
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) /*!< Line interrupt flag */ |
|||
/**
|
|||
* @brief DCMI MIS register |
|||
*/ |
|||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */ |
|||
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ |
|||
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ |
|||
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ |
|||
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset DCMI handle state
|
|||
* @param __HANDLE__ specifies the DCMI handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_DCMI_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
|
|||
/**
|
|||
* @brief Enable the DCMI. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) |
|||
|
|||
/**
|
|||
* @brief Disable the DCMI. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) |
|||
|
|||
/* Interrupt & Flag management */ |
|||
/**
|
|||
* @brief Get the DCMI pending flag. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @param __FLAG__ Get the specified flag. |
|||
* This parameter can be one of the following values (no combination allowed) |
|||
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) |
|||
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) |
|||
* @arg DCMI_FLAG_FNE: FIFO empty flag |
|||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask |
|||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask |
|||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask |
|||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask |
|||
* @arg DCMI_FLAG_LINERI: Line flag mask |
|||
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status |
|||
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status |
|||
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status |
|||
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status |
|||
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status |
|||
* @retval The state of FLAG. |
|||
*/ |
|||
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ |
|||
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ |
|||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) |
|||
|
|||
/**
|
|||
* @brief Clear the DCMI pending flags. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask |
|||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask |
|||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask |
|||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask |
|||
* @arg DCMI_FLAG_LINERI: Line flag mask |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Enable the specified DCMI interrupts. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask |
|||
* @arg DCMI_IT_OVR: Overrun interrupt mask |
|||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask |
|||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask |
|||
* @arg DCMI_IT_LINE: Line interrupt mask |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the specified DCMI interrupts. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask |
|||
* @arg DCMI_IT_OVR: Overrun interrupt mask |
|||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask |
|||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask |
|||
* @arg DCMI_IT_LINE: Line interrupt mask |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified DCMI interrupt has occurred or not. |
|||
* @param __HANDLE__ DCMI handle |
|||
* @param __INTERRUPT__ specifies the DCMI interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask |
|||
* @arg DCMI_IT_OVR: Overrun interrupt mask |
|||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask |
|||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask |
|||
* @arg DCMI_IT_LINE: Line interrupt mask |
|||
* @retval The state of INTERRUPT. |
|||
*/ |
|||
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
|
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions *****************************/ |
|||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); |
|||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); |
|||
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *****************************************************/ |
|||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); |
|||
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi); |
|||
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi); |
|||
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi); |
|||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ***********************************************/ |
|||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); |
|||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); |
|||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); |
|||
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions *************************************************/ |
|||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); |
|||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_MIS_INDEX 0x1000U /*!< DCMI MIS register index */ |
|||
#define DCMI_SR_INDEX 0x2000U /*!< DCMI SR register index */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private macro -------------------------------------------------------------*/ |
|||
/** @defgroup DCMI_Private_Macros DCMI Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \ |
|||
((MODE) == DCMI_MODE_SNAPSHOT)) |
|||
|
|||
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ |
|||
((MODE) == DCMI_SYNCHRO_EMBEDDED)) |
|||
|
|||
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \ |
|||
((POLARITY) == DCMI_PCKPOLARITY_RISING)) |
|||
|
|||
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \ |
|||
((POLARITY) == DCMI_VSPOLARITY_HIGH)) |
|||
|
|||
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \ |
|||
((POLARITY) == DCMI_HSPOLARITY_HIGH)) |
|||
|
|||
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \ |
|||
((JPEG_MODE) == DCMI_JPEG_ENABLE)) |
|||
|
|||
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \ |
|||
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \ |
|||
((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) |
|||
|
|||
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \ |
|||
((DATA) == DCMI_EXTEND_DATA_10B) || \ |
|||
((DATA) == DCMI_EXTEND_DATA_12B) || \ |
|||
((DATA) == DCMI_EXTEND_DATA_14B)) |
|||
|
|||
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) |
|||
|
|||
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
|||
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
|||
STM32F479xx */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_DCMI_H */ |
|||
@ -0,0 +1,208 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_dcmi_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of DCMI Extension HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file in |
|||
* the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_DCMI_EX_H |
|||
#define __STM32F4xx_HAL_DCMI_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
|||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ |
|||
defined(STM32F479xx) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup DCMIEx
|
|||
* @brief DCMI HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup DCMIEx_Exported_Types DCMI Extended Exported Types
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ |
|||
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ |
|||
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ |
|||
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ |
|||
}DCMI_CodesInitTypeDef; |
|||
|
|||
/**
|
|||
* @brief DCMI Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
|||
This parameter can be a value of @ref DCMI_Synchronization_Mode */ |
|||
|
|||
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
|||
This parameter can be a value of @ref DCMI_PIXCK_Polarity */ |
|||
|
|||
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
|||
This parameter can be a value of @ref DCMI_VSYNC_Polarity */ |
|||
|
|||
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
|||
This parameter can be a value of @ref DCMI_HSYNC_Polarity */ |
|||
|
|||
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
|
|||
This parameter can be a value of @ref DCMI_Capture_Rate */ |
|||
|
|||
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
|
|||
This parameter can be a value of @ref DCMI_Extended_Data_Mode */ |
|||
|
|||
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */ |
|||
|
|||
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode
|
|||
This parameter can be a value of @ref DCMI_MODE_JPEG */ |
|||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
|
|||
This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */ |
|||
|
|||
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
|
|||
This parameter can be a value of @ref DCMIEx_Byte_Select_Start */ |
|||
|
|||
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
|
|||
This parameter can be a value of @ref DCMIEx_Line_Select_Mode */ |
|||
|
|||
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
|
|||
This parameter can be a value of @ref DCMIEx_Line_Select_Start */ |
|||
|
|||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
}DCMI_InitTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_BSM_ALL 0x00000000U /*!< Interface captures all received data */ |
|||
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */ |
|||
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ |
|||
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_OEBS_ODD 0x00000000U /*!< Interface captures first data from the frame/line start, second one being dropped */ |
|||
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_LSM_ALL 0x00000000U /*!< Interface captures all received lines */ |
|||
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
|
|||
* @{ |
|||
*/ |
|||
#define DCMI_OELS_ODD 0x00000000U /*!< Interface captures first line from the frame start, second one being dropped */ |
|||
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
#define DCMI_POSITION_ESCR_LSC (uint32_t)DCMI_ESCR_LSC_Pos /*!< Required left shift to set line start delimiter */ |
|||
#define DCMI_POSITION_ESCR_LEC (uint32_t)DCMI_ESCR_LEC_Pos /*!< Required left shift to set line end delimiter */ |
|||
#define DCMI_POSITION_ESCR_FEC (uint32_t)DCMI_ESCR_FEC_Pos /*!< Required left shift to set frame end delimiter */ |
|||
|
|||
/* Private macro -------------------------------------------------------------*/ |
|||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \ |
|||
((MODE) == DCMI_BSM_OTHER) || \ |
|||
((MODE) == DCMI_BSM_ALTERNATE_4) || \ |
|||
((MODE) == DCMI_BSM_ALTERNATE_2)) |
|||
|
|||
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \ |
|||
((POLARITY) == DCMI_OEBS_EVEN)) |
|||
|
|||
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ |
|||
((MODE) == DCMI_LSM_ALTERNATE_2)) |
|||
|
|||
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ |
|||
((POLARITY) == DCMI_OELS_EVEN)) |
|||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
|||
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
|||
STM32F479xx */ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_DCMI_H */ |
|||
File diff suppressed because it is too large
@ -0,0 +1,638 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_dma2d.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of DMA2D HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_DMA2D_H |
|||
#define STM32F4xx_HAL_DMA2D_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (DMA2D) |
|||
|
|||
/** @addtogroup DMA2D DMA2D
|
|||
* @brief DMA2D HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
|
|||
* @{ |
|||
*/ |
|||
#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ |
|||
|
|||
/**
|
|||
* @brief DMA2D CLUT Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ |
|||
|
|||
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
|
|||
This parameter can be one value of @ref DMA2D_CLUT_CM. */ |
|||
|
|||
uint32_t Size; /*!< Configures the DMA2D CLUT size.
|
|||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ |
|||
} DMA2D_CLUTCfgTypeDef; |
|||
|
|||
/**
|
|||
* @brief DMA2D Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
|
|||
This parameter can be one value of @ref DMA2D_Mode. */ |
|||
|
|||
uint32_t ColorMode; /*!< Configures the color format of the output image.
|
|||
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ |
|||
|
|||
uint32_t OutputOffset; /*!< Specifies the Offset value.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
|||
|
|||
|
|||
|
|||
|
|||
} DMA2D_InitTypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @brief DMA2D Layer structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
|||
|
|||
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
|
|||
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ |
|||
|
|||
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
|
|||
This parameter can be one value of @ref DMA2D_Alpha_Mode. */ |
|||
|
|||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
|
|||
in case of A8 or A4 color mode. |
|||
This parameter must be a number between Min_Data = 0x00 |
|||
and Max_Data = 0xFF except for the color modes detailed below. |
|||
@note In case of A8 or A4 color mode (ARGB), |
|||
this parameter must be a number between |
|||
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where |
|||
- InputAlpha[24:31] is the alpha value ALPHA[0:7] |
|||
- InputAlpha[16:23] is the red value RED[0:7] |
|||
- InputAlpha[8:15] is the green value GREEN[0:7] |
|||
- InputAlpha[0:7] is the blue value BLUE[0:7]. */ |
|||
|
|||
|
|||
} DMA2D_LayerCfgTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL DMA2D State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ |
|||
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
|||
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
|||
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ |
|||
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ |
|||
} HAL_DMA2D_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief DMA2D handle Structure definition |
|||
*/ |
|||
typedef struct __DMA2D_HandleTypeDef |
|||
{ |
|||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ |
|||
|
|||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ |
|||
|
|||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ |
|||
|
|||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ |
|||
|
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) |
|||
void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ |
|||
|
|||
void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ |
|||
|
|||
void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ |
|||
|
|||
void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ |
|||
|
|||
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ |
|||
|
|||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */ |
|||
|
|||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */ |
|||
} DMA2D_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL DMA2D Callback pointer definition |
|||
*/ |
|||
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ |
|||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Error_Code DMA2D Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ |
|||
#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ |
|||
#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ |
|||
#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) |
|||
#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ |
|||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Mode DMA2D Mode
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ |
|||
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ |
|||
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ |
|||
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ |
|||
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ |
|||
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ |
|||
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ |
|||
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ |
|||
#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ |
|||
#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ |
|||
#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ |
|||
#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ |
|||
#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ |
|||
#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ |
|||
#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ |
|||
#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ |
|||
#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ |
|||
#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ |
|||
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ |
|||
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value |
|||
with original alpha channel value */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
|
|||
|
|||
|
|||
|
|||
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ |
|||
#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ |
|||
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ |
|||
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ |
|||
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ |
|||
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ |
|||
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Flags DMA2D Flags
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ |
|||
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ |
|||
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ |
|||
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ |
|||
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ |
|||
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL DMA2D common Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ |
|||
HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ |
|||
HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ |
|||
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ |
|||
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ |
|||
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ |
|||
} HAL_DMA2D_CallbackIDTypeDef; |
|||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported macros ------------------------------------------------------------*/ |
|||
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset DMA2D handle state
|
|||
* @param __HANDLE__ specifies the DMA2D handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
}while(0) |
|||
#else |
|||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) |
|||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
/**
|
|||
* @brief Enable the DMA2D. |
|||
* @param __HANDLE__ DMA2D handle |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) |
|||
|
|||
|
|||
/* Interrupt & Flag management */ |
|||
/**
|
|||
* @brief Get the DMA2D pending flags. |
|||
* @param __HANDLE__ DMA2D handle |
|||
* @param __FLAG__ flag to check. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DMA2D_FLAG_CE: Configuration error flag |
|||
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
|||
* @arg DMA2D_FLAG_CAE: CLUT access error flag |
|||
* @arg DMA2D_FLAG_TW: Transfer Watermark flag |
|||
* @arg DMA2D_FLAG_TC: Transfer complete flag |
|||
* @arg DMA2D_FLAG_TE: Transfer error flag |
|||
* @retval The state of FLAG. |
|||
*/ |
|||
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the DMA2D pending flags. |
|||
* @param __HANDLE__ DMA2D handle |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DMA2D_FLAG_CE: Configuration error flag |
|||
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
|||
* @arg DMA2D_FLAG_CAE: CLUT access error flag |
|||
* @arg DMA2D_FLAG_TW: Transfer Watermark flag |
|||
* @arg DMA2D_FLAG_TC: Transfer complete flag |
|||
* @arg DMA2D_FLAG_TE: Transfer error flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Enable the specified DMA2D interrupts. |
|||
* @param __HANDLE__ DMA2D handle |
|||
* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DMA2D_IT_CE: Configuration error interrupt mask |
|||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
|||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
|||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
|||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask |
|||
* @arg DMA2D_IT_TE: Transfer error interrupt mask |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the specified DMA2D interrupts. |
|||
* @param __HANDLE__ DMA2D handle |
|||
* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg DMA2D_IT_CE: Configuration error interrupt mask |
|||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
|||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
|||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
|||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask |
|||
* @arg DMA2D_IT_TE: Transfer error interrupt mask |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified DMA2D interrupt source is enabled or not. |
|||
* @param __HANDLE__ DMA2D handle |
|||
* @param __INTERRUPT__ specifies the DMA2D interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg DMA2D_IT_CE: Configuration error interrupt mask |
|||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
|||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
|||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
|||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask |
|||
* @arg DMA2D_IT_TE: Transfer error interrupt mask |
|||
* @retval The state of INTERRUPT source. |
|||
*/ |
|||
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization and de-initialization functions *******************************/ |
|||
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); |
|||
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); |
|||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); |
|||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, |
|||
pDMA2D_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* IO operation functions *******************************************************/ |
|||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, |
|||
uint32_t Height); |
|||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, |
|||
uint32_t DstAddress, uint32_t Width, uint32_t Height); |
|||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, |
|||
uint32_t Height); |
|||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, |
|||
uint32_t DstAddress, uint32_t Width, uint32_t Height); |
|||
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); |
|||
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); |
|||
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); |
|||
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, |
|||
uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, |
|||
uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); |
|||
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); |
|||
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); |
|||
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); |
|||
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
|||
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
|||
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Peripheral State functions ***************************************************/ |
|||
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); |
|||
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Color_Value DMA2D Color Value
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Layers DMA2D Layers
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ |
|||
#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Offset DMA2D Offset
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_Size DMA2D Size
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ |
|||
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
|
|||
* @{ |
|||
*/ |
|||
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ |
|||
|| ((LAYER) == DMA2D_FOREGROUND_LAYER)) |
|||
|
|||
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ |
|||
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) |
|||
|
|||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ |
|||
((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ |
|||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ |
|||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ |
|||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) |
|||
|
|||
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) |
|||
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) |
|||
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) |
|||
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) |
|||
|
|||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_RGB888) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_RGB565) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_L8) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_AL44) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_AL88) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_L4) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_A8) || \ |
|||
((INPUT_CM) == DMA2D_INPUT_A4)) |
|||
|
|||
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ |
|||
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ |
|||
((AlphaMode) == DMA2D_COMBINE_ALPHA)) |
|||
|
|||
|
|||
|
|||
|
|||
|
|||
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) |
|||
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) |
|||
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) |
|||
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ |
|||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ |
|||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) |
|||
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ |
|||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ |
|||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* defined (DMA2D) */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_DMA2D_H */ |
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1,841 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_fmpi2c.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of FMPI2C HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_FMPI2C_H |
|||
#define STM32F4xx_HAL_FMPI2C_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMPI2C_CR1_PE) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2C
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition
|
|||
* @brief FMPI2C Configuration Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
|
|||
This parameter calculated by referring to FMPI2C initialization section |
|||
in Reference manual */ |
|||
|
|||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
|||
This parameter can be a 7-bit or 10-bit address. */ |
|||
|
|||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
|||
This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */ |
|||
|
|||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
|||
This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */ |
|||
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
|||
This parameter can be a 7-bit address. */ |
|||
|
|||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
|||
mode is selected. |
|||
This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */ |
|||
|
|||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
|||
This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */ |
|||
|
|||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
|||
This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ |
|||
|
|||
} FMPI2C_InitTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
|||
* @brief HAL State structure definition |
|||
* @note HAL FMPI2C State value coding follow below described bitmap :\n |
|||
* b7-b6 Error information\n |
|||
* 00 : No Error\n |
|||
* 01 : Abort (Abort user request on going)\n |
|||
* 10 : Timeout\n |
|||
* 11 : Error\n |
|||
* b5 Peripheral initialization status\n |
|||
* 0 : Reset (peripheral not initialized)\n |
|||
* 1 : Init done (peripheral initialized and ready to use. HAL FMPI2C Init function called)\n |
|||
* b4 (not used)\n |
|||
* x : Should be set to 0\n |
|||
* b3\n |
|||
* 0 : Ready or Busy (No Listen mode ongoing)\n |
|||
* 1 : Listen (peripheral in Address Listen Mode)\n |
|||
* b2 Intrinsic process state\n |
|||
* 0 : Ready\n |
|||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n |
|||
* b1 Rx state\n |
|||
* 0 : Ready (no Rx operation ongoing)\n |
|||
* 1 : Busy (Rx operation ongoing)\n |
|||
* b0 Tx state\n |
|||
* 0 : Ready (no Tx operation ongoing)\n |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_FMPI2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ |
|||
HAL_FMPI2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_FMPI2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ |
|||
HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ |
|||
HAL_FMPI2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
|||
HAL_FMPI2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ |
|||
HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
|||
process is ongoing */ |
|||
HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
|||
process is ongoing */ |
|||
HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ |
|||
HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ |
|||
HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */ |
|||
|
|||
} HAL_FMPI2C_StateTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
|||
* @brief HAL Mode structure definition |
|||
* @note HAL FMPI2C Mode value coding follow below described bitmap :\n |
|||
* b7 (not used)\n |
|||
* x : Should be set to 0\n |
|||
* b6\n |
|||
* 0 : None\n |
|||
* 1 : Memory (HAL FMPI2C communication is in Memory Mode)\n |
|||
* b5\n |
|||
* 0 : None\n |
|||
* 1 : Slave (HAL FMPI2C communication is in Slave Mode)\n |
|||
* b4\n |
|||
* 0 : None\n |
|||
* 1 : Master (HAL FMPI2C communication is in Master Mode)\n |
|||
* b3-b2-b1-b0 (not used)\n |
|||
* xxxx : Should be set to 0000 |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_FMPI2C_MODE_NONE = 0x00U, /*!< No FMPI2C communication on going */ |
|||
HAL_FMPI2C_MODE_MASTER = 0x10U, /*!< FMPI2C communication is in Master Mode */ |
|||
HAL_FMPI2C_MODE_SLAVE = 0x20U, /*!< FMPI2C communication is in Slave Mode */ |
|||
HAL_FMPI2C_MODE_MEM = 0x40U /*!< FMPI2C communication is in Memory Mode */ |
|||
|
|||
} HAL_FMPI2C_ModeTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition
|
|||
* @brief FMPI2C Error Code definition |
|||
* @{ |
|||
*/ |
|||
#define HAL_FMPI2C_ERROR_NONE (0x00000000U) /*!< No error */ |
|||
#define HAL_FMPI2C_ERROR_BERR (0x00000001U) /*!< BERR error */ |
|||
#define HAL_FMPI2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ |
|||
#define HAL_FMPI2C_ERROR_AF (0x00000004U) /*!< ACKF error */ |
|||
#define HAL_FMPI2C_ERROR_OVR (0x00000008U) /*!< OVR error */ |
|||
#define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
|||
#define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ |
|||
#define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ |
|||
#define HAL_FMPI2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ |
|||
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) |
|||
#define HAL_FMPI2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ |
|||
#define HAL_FMPI2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition
|
|||
* @brief FMPI2C handle Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct __FMPI2C_HandleTypeDef |
|||
{ |
|||
FMPI2C_TypeDef *Instance; /*!< FMPI2C registers base address */ |
|||
|
|||
FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */ |
|||
|
|||
uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */ |
|||
|
|||
uint16_t XferSize; /*!< FMPI2C transfer size */ |
|||
|
|||
__IO uint16_t XferCount; /*!< FMPI2C transfer counter */ |
|||
|
|||
__IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can
|
|||
be a value of @ref FMPI2C_XFEROPTIONS */ |
|||
|
|||
__IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */ |
|||
|
|||
HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); |
|||
/*!< FMPI2C transfer IRQ handler function pointer */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< FMPI2C locking object */ |
|||
|
|||
__IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */ |
|||
|
|||
__IO HAL_FMPI2C_ModeTypeDef Mode; /*!< FMPI2C communication mode */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< FMPI2C Error code */ |
|||
|
|||
__IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ |
|||
|
|||
__IO uint32_t Devaddress; /*!< FMPI2C Target device address */ |
|||
|
|||
__IO uint32_t Memaddress; /*!< FMPI2C Target memory address */ |
|||
|
|||
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) |
|||
void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Master Tx Transfer completed callback */ |
|||
void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Master Rx Transfer completed callback */ |
|||
void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Slave Tx Transfer completed callback */ |
|||
void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Slave Rx Transfer completed callback */ |
|||
void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Listen Complete callback */ |
|||
void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Memory Tx Transfer completed callback */ |
|||
void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Memory Rx Transfer completed callback */ |
|||
void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Error callback */ |
|||
void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Abort callback */ |
|||
|
|||
void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
/*!< FMPI2C Slave Address Match callback */ |
|||
|
|||
void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< FMPI2C Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ |
|||
} FMPI2C_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL FMPI2C Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPI2C Master Tx Transfer completed callback ID */ |
|||
HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPI2C Master Rx Transfer completed callback ID */ |
|||
HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPI2C Slave Tx Transfer completed callback ID */ |
|||
HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPI2C Slave Rx Transfer completed callback ID */ |
|||
HAL_FMPI2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPI2C Listen Complete callback ID */ |
|||
HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< FMPI2C Memory Tx Transfer callback ID */ |
|||
HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< FMPI2C Memory Rx Transfer completed callback ID */ |
|||
HAL_FMPI2C_ERROR_CB_ID = 0x07U, /*!< FMPI2C Error callback ID */ |
|||
HAL_FMPI2C_ABORT_CB_ID = 0x08U, /*!< FMPI2C Abort callback ID */ |
|||
|
|||
HAL_FMPI2C_MSPINIT_CB_ID = 0x09U, /*!< FMPI2C Msp Init callback ID */ |
|||
HAL_FMPI2C_MSPDEINIT_CB_ID = 0x0AU /*!< FMPI2C Msp DeInit callback ID */ |
|||
|
|||
} HAL_FMPI2C_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL FMPI2C Callback pointer definition |
|||
*/ |
|||
typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/*!< pointer to an FMPI2C callback function */ |
|||
typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, |
|||
uint16_t AddrMatchCode); |
|||
/*!< pointer to an FMPI2C Address Match callback function */ |
|||
|
|||
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_XFEROPTIONS FMPI2C Sequential Transfer Options
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE) |
|||
#define FMPI2C_FIRST_AND_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE)) |
|||
#define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE)) |
|||
#define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) |
|||
#define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) |
|||
#define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE) |
|||
|
|||
/* List of XferOptions in usage of :
|
|||
* 1- Restart condition in all use cases (direction change or not) |
|||
*/ |
|||
#define FMPI2C_OTHER_FRAME (0x000000AAU) |
|||
#define FMPI2C_OTHER_AND_LAST_FRAME (0x0000AA00U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_ADDRESSINGMODE_7BIT (0x00000001U) |
|||
#define FMPI2C_ADDRESSINGMODE_10BIT (0x00000002U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_DUALADDRESS_DISABLE (0x00000000U) |
|||
#define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_OA2_NOMASK ((uint8_t)0x00U) |
|||
#define FMPI2C_OA2_MASK01 ((uint8_t)0x01U) |
|||
#define FMPI2C_OA2_MASK02 ((uint8_t)0x02U) |
|||
#define FMPI2C_OA2_MASK03 ((uint8_t)0x03U) |
|||
#define FMPI2C_OA2_MASK04 ((uint8_t)0x04U) |
|||
#define FMPI2C_OA2_MASK05 ((uint8_t)0x05U) |
|||
#define FMPI2C_OA2_MASK06 ((uint8_t)0x06U) |
|||
#define FMPI2C_OA2_MASK07 ((uint8_t)0x07U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_GENERALCALL_DISABLE (0x00000000U) |
|||
#define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_NOSTRETCH_DISABLE (0x00000000U) |
|||
#define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_MEMADD_SIZE_8BIT (0x00000001U) |
|||
#define FMPI2C_MEMADD_SIZE_16BIT (0x00000002U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_XFERDIRECTION FMPI2C Transfer Direction Master Point of View
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_DIRECTION_TRANSMIT (0x00000000U) |
|||
#define FMPI2C_DIRECTION_RECEIVE (0x00000001U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_RELOAD_END_MODE FMPI2C Reload End Mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD |
|||
#define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND |
|||
#define FMPI2C_SOFTEND_MODE (0x00000000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_NO_STARTSTOP (0x00000000U) |
|||
#define FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) |
|||
#define FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) |
|||
#define FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition
|
|||
* @brief FMPI2C Interrupt definition |
|||
* Elements values convention: 0xXXXXXXXX |
|||
* - XXXXXXXX : Interrupt control mask |
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE |
|||
#define FMPI2C_IT_TCI FMPI2C_CR1_TCIE |
|||
#define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE |
|||
#define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE |
|||
#define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE |
|||
#define FMPI2C_IT_RXI FMPI2C_CR1_RXIE |
|||
#define FMPI2C_IT_TXI FMPI2C_CR1_TXIE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE |
|||
#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS |
|||
#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE |
|||
#define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR |
|||
#define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF |
|||
#define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF |
|||
#define FMPI2C_FLAG_TC FMPI2C_ISR_TC |
|||
#define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR |
|||
#define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR |
|||
#define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO |
|||
#define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR |
|||
#define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR |
|||
#define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT |
|||
#define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT |
|||
#define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY |
|||
#define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
|
|||
/** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset FMPI2C handle state.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET) |
|||
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Enable the specified FMPI2C interrupt.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPI2C_IT_ERRI Errors interrupt enable |
|||
* @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable |
|||
* @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable |
|||
* @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable |
|||
* @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable |
|||
* @arg @ref FMPI2C_IT_RXI RX interrupt enable |
|||
* @arg @ref FMPI2C_IT_TXI TX interrupt enable |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
|||
|
|||
/** @brief Disable the specified FMPI2C interrupt.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPI2C_IT_ERRI Errors interrupt enable |
|||
* @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable |
|||
* @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable |
|||
* @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable |
|||
* @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable |
|||
* @arg @ref FMPI2C_IT_RXI RX interrupt enable |
|||
* @arg @ref FMPI2C_IT_TXI TX interrupt enable |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
|||
|
|||
/** @brief Check whether the specified FMPI2C interrupt source is enabled or not.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @param __INTERRUPT__ specifies the FMPI2C interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPI2C_IT_ERRI Errors interrupt enable |
|||
* @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable |
|||
* @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable |
|||
* @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable |
|||
* @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable |
|||
* @arg @ref FMPI2C_IT_RXI RX interrupt enable |
|||
* @arg @ref FMPI2C_IT_TXI TX interrupt enable |
|||
* |
|||
* @retval The new state of __INTERRUPT__ (SET or RESET). |
|||
*/ |
|||
#define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ |
|||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Check whether the specified FMPI2C flag is set or not.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPI2C_FLAG_TXE Transmit data register empty |
|||
* @arg @ref FMPI2C_FLAG_TXIS Transmit interrupt status |
|||
* @arg @ref FMPI2C_FLAG_RXNE Receive data register not empty |
|||
* @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode) |
|||
* @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag |
|||
* @arg @ref FMPI2C_FLAG_STOPF STOP detection flag |
|||
* @arg @ref FMPI2C_FLAG_TC Transfer complete (master mode) |
|||
* @arg @ref FMPI2C_FLAG_TCR Transfer complete reload |
|||
* @arg @ref FMPI2C_FLAG_BERR Bus error |
|||
* @arg @ref FMPI2C_FLAG_ARLO Arbitration lost |
|||
* @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun |
|||
* @arg @ref FMPI2C_FLAG_PECERR PEC error in reception |
|||
* @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag |
|||
* @arg @ref FMPI2C_FLAG_ALERT SMBus alert |
|||
* @arg @ref FMPI2C_FLAG_BUSY Bus busy |
|||
* @arg @ref FMPI2C_FLAG_DIR Transfer direction (slave mode) |
|||
* |
|||
* @retval The new state of __FLAG__ (SET or RESET). |
|||
*/ |
|||
#define FMPI2C_FLAG_MASK (0x0001FFFFU) |
|||
#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ |
|||
(__FLAG__)) == (__FLAG__)) ? SET : RESET) |
|||
|
|||
/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg @ref FMPI2C_FLAG_TXE Transmit data register empty |
|||
* @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode) |
|||
* @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag |
|||
* @arg @ref FMPI2C_FLAG_STOPF STOP detection flag |
|||
* @arg @ref FMPI2C_FLAG_BERR Bus error |
|||
* @arg @ref FMPI2C_FLAG_ARLO Arbitration lost |
|||
* @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun |
|||
* @arg @ref FMPI2C_FLAG_PECERR PEC error in reception |
|||
* @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag |
|||
* @arg @ref FMPI2C_FLAG_ALERT SMBus alert |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \ |
|||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ |
|||
((__HANDLE__)->Instance->ICR = (__FLAG__))) |
|||
|
|||
/** @brief Enable the specified FMPI2C peripheral.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) |
|||
|
|||
/** @brief Disable the specified FMPI2C peripheral.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) |
|||
|
|||
/** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode.
|
|||
* @param __HANDLE__ specifies the FMPI2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include FMPI2C HAL Extended module */ |
|||
#include "stm32f4xx_hal_fmpi2c_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup FMPI2C_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions******************************/ |
|||
HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, |
|||
pFMPI2C_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions ****************************************************/ |
|||
/******* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, |
|||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, |
|||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, |
|||
uint32_t Timeout); |
|||
|
|||
/******* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, |
|||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, |
|||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, |
|||
uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, |
|||
uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress); |
|||
|
|||
/******* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, |
|||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, |
|||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, |
|||
uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, |
|||
uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, |
|||
uint32_t XferOptions); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|||
* @{ |
|||
*/ |
|||
/******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
|||
void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State, Mode and Error functions *********************************/ |
|||
HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \ |
|||
((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) |
|||
|
|||
#define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \ |
|||
((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) |
|||
|
|||
#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \ |
|||
((MASK) == FMPI2C_OA2_MASK01) || \ |
|||
((MASK) == FMPI2C_OA2_MASK02) || \ |
|||
((MASK) == FMPI2C_OA2_MASK03) || \ |
|||
((MASK) == FMPI2C_OA2_MASK04) || \ |
|||
((MASK) == FMPI2C_OA2_MASK05) || \ |
|||
((MASK) == FMPI2C_OA2_MASK06) || \ |
|||
((MASK) == FMPI2C_OA2_MASK07)) |
|||
|
|||
#define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \ |
|||
((CALL) == FMPI2C_GENERALCALL_ENABLE)) |
|||
|
|||
#define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \ |
|||
((STRETCH) == FMPI2C_NOSTRETCH_ENABLE)) |
|||
|
|||
#define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \ |
|||
((SIZE) == FMPI2C_MEMADD_SIZE_16BIT)) |
|||
|
|||
#define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \ |
|||
((MODE) == FMPI2C_AUTOEND_MODE) || \ |
|||
((MODE) == FMPI2C_SOFTEND_MODE)) |
|||
|
|||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPI2C_GENERATE_STOP) || \ |
|||
((REQUEST) == FMPI2C_GENERATE_START_READ) || \ |
|||
((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \ |
|||
((REQUEST) == FMPI2C_NO_STARTSTOP)) |
|||
|
|||
#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \ |
|||
((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ |
|||
((REQUEST) == FMPI2C_NEXT_FRAME) || \ |
|||
((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ |
|||
((REQUEST) == FMPI2C_LAST_FRAME) || \ |
|||
((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \ |
|||
IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) |
|||
|
|||
#define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \ |
|||
((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) |
|||
|
|||
#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ |
|||
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ |
|||
FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ |
|||
FMPI2C_CR2_RD_WRN))) |
|||
|
|||
#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ |
|||
>> 16U)) |
|||
#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ |
|||
>> 16U)) |
|||
#define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) |
|||
#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) |
|||
#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) |
|||
|
|||
#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
|||
#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
|||
|
|||
#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ |
|||
(uint16_t)(0xFF00U))) >> 8U))) |
|||
#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) |
|||
|
|||
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \ |
|||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ |
|||
(FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ |
|||
(~FMPI2C_CR2_RD_WRN)) : \ |
|||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ |
|||
(FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \ |
|||
(~FMPI2C_CR2_RD_WRN))) |
|||
|
|||
#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ |
|||
((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) |
|||
#define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private Functions ---------------------------------------------------------*/ |
|||
/** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
|
|||
* @{ |
|||
*/ |
|||
/* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMPI2C_CR1_PE */ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_FMPI2C_H */ |
|||
@ -0,0 +1,150 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_fmpi2c_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of FMPI2C HAL Extended module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_FMPI2C_EX_H |
|||
#define STM32F4xx_HAL_FMPI2C_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMPI2C_CR1_PE) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2CEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup FMPI2CEx_Exported_Constants FMPI2C Extended Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2CEx_Analog_Filter FMPI2C Extended Analog Filter
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_ANALOGFILTER_ENABLE 0x00000000U |
|||
#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPI2CEx_FastModePlus FMPI2C Extended Fast Mode Plus
|
|||
* @{ |
|||
*/ |
|||
#define FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */ |
|||
#define FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup FMPI2CEx_Exported_Macros FMPI2C Extended Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Filter Mode Functions
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ************************************************/ |
|||
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter); |
|||
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPI2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
|||
* @{ |
|||
*/ |
|||
void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); |
|||
void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup FMPI2CEx_Private_Constants FMPI2C Extended Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup FMPI2CEx_Private_Macro FMPI2C Extended Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \ |
|||
((FILTER) == FMPI2C_ANALOGFILTER_DISABLE)) |
|||
|
|||
#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
|||
|
|||
#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \ |
|||
(((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private Functions ---------------------------------------------------------*/ |
|||
/** @defgroup FMPI2CEx_Private_Functions FMPI2C Extended Private Functions
|
|||
* @{ |
|||
*/ |
|||
/* Private functions are defined in stm32f4xx_hal_fmpi2c_ex.c file */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMPI2C_CR1_PE */ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_FMPI2C_EX_H */ |
|||
@ -0,0 +1,793 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_fmpsmbus.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of FMPSMBUS HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_FMPSMBUS_H |
|||
#define STM32F4xx_HAL_FMPSMBUS_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMPI2C_CR1_PE) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUS
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition
|
|||
* @brief FMPSMBUS Configuration Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value.
|
|||
This parameter calculated by referring to FMPSMBUS initialization section |
|||
in Reference manual */ |
|||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
|||
This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ |
|||
|
|||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
|||
This parameter can be a 7-bit or 10-bit address. */ |
|||
|
|||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
|||
This parameter can be a value of @ref FMPSMBUS_addressing_mode */ |
|||
|
|||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
|||
This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ |
|||
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
|||
This parameter can be a 7-bit address. */ |
|||
|
|||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
|
|||
if dual addressing mode is selected |
|||
This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ |
|||
|
|||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
|||
This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ |
|||
|
|||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
|||
This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ |
|||
|
|||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
|||
This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ |
|||
|
|||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
|||
This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ |
|||
|
|||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value.
|
|||
(Enable bits and different timeout values) |
|||
This parameter calculated by referring to FMPSMBUS initialization section |
|||
in Reference manual */ |
|||
} FMPSMBUS_InitTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_state_definition HAL state definition
|
|||
* @brief HAL State definition |
|||
* @{ |
|||
*/ |
|||
#define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ |
|||
#define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ |
|||
#define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ |
|||
#define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ |
|||
#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ |
|||
#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ |
|||
#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ |
|||
#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ |
|||
#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ |
|||
#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition
|
|||
* @brief FMPSMBUS Error Code definition |
|||
* @{ |
|||
*/ |
|||
#define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ |
|||
#define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ |
|||
#define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ |
|||
#define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ |
|||
#define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ |
|||
#define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ |
|||
#define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ |
|||
#define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ |
|||
#define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ |
|||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) |
|||
#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ |
|||
#define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition
|
|||
* @brief FMPSMBUS handle Structure definition |
|||
* @{ |
|||
*/ |
|||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) |
|||
typedef struct __FMPSMBUS_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ |
|||
{ |
|||
FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ |
|||
|
|||
FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ |
|||
|
|||
uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ |
|||
|
|||
uint16_t XferSize; /*!< FMPSMBUS transfer size */ |
|||
|
|||
__IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ |
|||
|
|||
__IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ |
|||
|
|||
__IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ |
|||
|
|||
__IO uint32_t State; /*!< FMPSMBUS communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ |
|||
|
|||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) |
|||
void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Master Tx Transfer completed callback */ |
|||
void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Master Rx Transfer completed callback */ |
|||
void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Slave Tx Transfer completed callback */ |
|||
void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Slave Rx Transfer completed callback */ |
|||
void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Listen Complete callback */ |
|||
void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Error callback */ |
|||
|
|||
void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
/*!< FMPSMBUS Slave Address Match callback */ |
|||
|
|||
void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< FMPSMBUS Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ |
|||
} FMPSMBUS_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL FMPSMBUS Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ |
|||
HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ |
|||
HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ |
|||
HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ |
|||
HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ |
|||
HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ |
|||
|
|||
HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ |
|||
HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ |
|||
|
|||
} HAL_FMPSMBUS_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL FMPSMBUS Callback pointer definition |
|||
*/ |
|||
typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/*!< pointer to an FMPSMBUS callback function */ |
|||
typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, |
|||
uint16_t AddrMatchCode); |
|||
/*!< pointer to an FMPSMBUS Address Match callback function */ |
|||
|
|||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) |
|||
#define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) |
|||
#define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) |
|||
#define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) |
|||
#define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) |
|||
#define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) |
|||
#define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) |
|||
#define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) |
|||
#define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) |
|||
#define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) |
|||
#define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) |
|||
#define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) |
|||
#define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_PEC_DISABLE (0x00000000U) |
|||
#define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN |
|||
#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) |
|||
#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define FMPSMBUS_SOFTEND_MODE (0x00000000U) |
|||
#define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD |
|||
#define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND |
|||
#define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define FMPSMBUS_NO_STARTSTOP (0x00000000U) |
|||
#define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) |
|||
#define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) |
|||
#define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* List of XferOptions in usage of :
|
|||
* 1- Restart condition when direction change |
|||
* 2- No Restart condition in other use cases |
|||
*/ |
|||
#define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE |
|||
#define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) |
|||
#define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE |
|||
#define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE |
|||
#define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) |
|||
#define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) |
|||
#define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) |
|||
|
|||
/* List of XferOptions in usage of :
|
|||
* 1- Restart condition in all use cases (direction change or not) |
|||
*/ |
|||
#define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) |
|||
#define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) |
|||
#define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) |
|||
#define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition
|
|||
* @brief FMPSMBUS Interrupt definition |
|||
* Elements values convention: 0xXXXXXXXX |
|||
* - XXXXXXXX : Interrupt control mask |
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE |
|||
#define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE |
|||
#define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE |
|||
#define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE |
|||
#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE |
|||
#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE |
|||
#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE |
|||
#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ |
|||
FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) |
|||
#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ |
|||
FMPSMBUS_IT_RXI) |
|||
#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) |
|||
#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition
|
|||
* @brief Flag definition |
|||
* Elements values convention: 0xXXXXYYYY |
|||
* - XXXXXXXX : Flag mask |
|||
* @{ |
|||
*/ |
|||
|
|||
#define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE |
|||
#define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS |
|||
#define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE |
|||
#define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR |
|||
#define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF |
|||
#define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF |
|||
#define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC |
|||
#define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR |
|||
#define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR |
|||
#define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO |
|||
#define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR |
|||
#define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR |
|||
#define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT |
|||
#define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT |
|||
#define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY |
|||
#define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros ------------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset FMPSMBUS handle state.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) |
|||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Enable the specified FMPSMBUS interrupts.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_RXI RX interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_TXI TX interrupt enable |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
|||
|
|||
/** @brief Disable the specified FMPSMBUS interrupts.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_RXI RX interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_TXI TX interrupt enable |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
|||
|
|||
/** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_RXI RX interrupt enable |
|||
* @arg @ref FMPSMBUS_IT_TXI TX interrupt enable |
|||
* |
|||
* @retval The new state of __IT__ (SET or RESET). |
|||
*/ |
|||
#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
|||
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Check whether the specified FMPSMBUS flag is set or not.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty |
|||
* @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status |
|||
* @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty |
|||
* @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) |
|||
* @arg @ref FMPSMBUS_FLAG_AF NACK received flag |
|||
* @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag |
|||
* @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) |
|||
* @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload |
|||
* @arg @ref FMPSMBUS_FLAG_BERR Bus error |
|||
* @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost |
|||
* @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun |
|||
* @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception |
|||
* @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
|||
* @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert |
|||
* @arg @ref FMPSMBUS_FLAG_BUSY Bus busy |
|||
* @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) |
|||
* |
|||
* @retval The new state of __FLAG__ (SET or RESET). |
|||
*/ |
|||
#define FMPSMBUS_FLAG_MASK (0x0001FFFFU) |
|||
#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ |
|||
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ |
|||
((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) |
|||
|
|||
/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty |
|||
* @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) |
|||
* @arg @ref FMPSMBUS_FLAG_AF NACK received flag |
|||
* @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag |
|||
* @arg @ref FMPSMBUS_FLAG_BERR Bus error |
|||
* @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost |
|||
* @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun |
|||
* @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception |
|||
* @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
|||
* @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPSMBUS_FLAG_TXE) ? \ |
|||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ |
|||
((__HANDLE__)->Instance->ICR = (__FLAG__))) |
|||
|
|||
/** @brief Enable the specified FMPSMBUS peripheral.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) |
|||
|
|||
/** @brief Disable the specified FMPSMBUS peripheral.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) |
|||
|
|||
/** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode.
|
|||
* @param __HANDLE__ specifies the FMPSMBUS Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ |
|||
((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) |
|||
|
|||
#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
|||
|
|||
#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ |
|||
((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) |
|||
|
|||
#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ |
|||
((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) |
|||
|
|||
#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK01) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK02) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK03) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK04) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK05) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK06) || \ |
|||
((MASK) == FMPSMBUS_OA2_MASK07)) |
|||
|
|||
#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ |
|||
((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) |
|||
|
|||
#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ |
|||
((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) |
|||
|
|||
#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ |
|||
((PEC) == FMPSMBUS_PEC_ENABLE)) |
|||
|
|||
#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ |
|||
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ |
|||
((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) |
|||
|
|||
#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ |
|||
((MODE) == FMPSMBUS_AUTOEND_MODE) || \ |
|||
((MODE) == FMPSMBUS_SOFTEND_MODE) || \ |
|||
((MODE) == FMPSMBUS_SENDPEC_MODE) || \ |
|||
((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ |
|||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ |
|||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ |
|||
((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ |
|||
FMPSMBUS_RELOAD_MODE ))) |
|||
|
|||
|
|||
#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ |
|||
((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ |
|||
((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ |
|||
((REQUEST) == FMPSMBUS_NO_STARTSTOP)) |
|||
|
|||
|
|||
#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ |
|||
((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ |
|||
((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ |
|||
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) |
|||
|
|||
#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ |
|||
((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) |
|||
|
|||
#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ |
|||
(uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ |
|||
FMPI2C_CR1_PECEN))) |
|||
#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ |
|||
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ |
|||
FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ |
|||
FMPI2C_CR2_RD_WRN))) |
|||
|
|||
#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ |
|||
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ |
|||
(FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ |
|||
(~FMPI2C_CR2_RD_WRN)) : \ |
|||
(uint32_t)((((uint32_t)(__ADDRESS__) & \ |
|||
(FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ |
|||
(FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) |
|||
|
|||
#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) |
|||
#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) |
|||
#define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) |
|||
#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) |
|||
#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) |
|||
|
|||
#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ |
|||
((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) |
|||
#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
|||
|
|||
#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
|||
#define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include FMPSMBUS HAL Extended module */ |
|||
#include "stm32f4xx_hal_fmpsmbus_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization and de-initialization functions ****************************/ |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, |
|||
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, |
|||
pFMPSMBUS_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, |
|||
HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, |
|||
pFMPSMBUS_AddrCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* IO operation functions *****************************************************/ |
|||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
|||
* @{ |
|||
*/ |
|||
/******* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, |
|||
uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
|||
* @{ |
|||
*/ |
|||
/******* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, |
|||
uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, |
|||
uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, |
|||
uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, |
|||
uint32_t XferOptions); |
|||
|
|||
HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|||
* @{ |
|||
*/ |
|||
/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
|||
void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Peripheral State and Errors functions **************************************************/ |
|||
uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private Functions ---------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
|
|||
* @{ |
|||
*/ |
|||
/* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMPI2C_CR1_PE */ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_FMPSMBUS_H */ |
|||
@ -0,0 +1,136 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_fmpsmbus_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of FMPSMBUS HAL Extended module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_FMPSMBUS_EX_H |
|||
#define STM32F4xx_HAL_FMPSMBUS_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMPI2C_CR1_PE) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUSEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUSEx_Exported_Constants FMPSMBUS Extended Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup FMPSMBUSEx_FastModePlus FMPSMBUS Extended Fast Mode Plus
|
|||
* @{ |
|||
*/ |
|||
#define FMPSMBUS_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins */ |
|||
#define FMPSMBUS_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUSEx_Exported_Macros FMPSMBUS Extended Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup FMPSMBUSEx_Exported_Functions FMPSMBUS Extended Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ************************************************/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
|||
* @{ |
|||
*/ |
|||
void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); |
|||
void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUSEx_Private_Constants FMPSMBUS Extended Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUSEx_Private_Macro FMPSMBUS Extended Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \ |
|||
FMPSMBUS_FASTMODEPLUS_SCL) || \ |
|||
(((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ |
|||
FMPSMBUS_FASTMODEPLUS_SDA)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private Functions ---------------------------------------------------------*/ |
|||
/** @defgroup FMPSMBUSEx_Private_Functions FMPSMBUS Extended Private Functions
|
|||
* @{ |
|||
*/ |
|||
/* Private functions are defined in stm32f4xx_hal_fmpsmbus_ex.c file */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMPI2C_CR1_PE */ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */ |
|||
@ -0,0 +1,634 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_hash.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of HASH HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_HASH_H |
|||
#define STM32F4xx_HAL_HASH_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (HASH) |
|||
/** @addtogroup HASH
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup HASH_Exported_Types HASH Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HASH Configuration Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
|
|||
This parameter can be a value of @ref HASH_Data_Type. */ |
|||
|
|||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ |
|||
|
|||
uint8_t *pKey; /*!< The key is used only in HMAC operation. */ |
|||
|
|||
} HASH_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ |
|||
HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */ |
|||
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ |
|||
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */ |
|||
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */ |
|||
} HAL_HASH_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL phase structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */ |
|||
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */ |
|||
HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
|
|||
(step 1 consists in entering the inner hash function key) */ |
|||
HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
|
|||
(step 2 consists in entering the message text) */ |
|||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
|||
(step 3 consists in entering the outer hash function key) */ |
|||
} HAL_HASH_PhaseTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL HASH mode suspend definitions |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ |
|||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ |
|||
} HAL_HASH_SuspendTypeDef; |
|||
|
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) |
|||
/**
|
|||
* @brief HAL HASH common Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */ |
|||
HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */ |
|||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ |
|||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ |
|||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ |
|||
} HAL_HASH_CallbackIDTypeDef; |
|||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
/**
|
|||
* @brief HASH Handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) |
|||
typedef struct __HASH_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ |
|||
{ |
|||
HASH_InitTypeDef Init; /*!< HASH required parameters */ |
|||
|
|||
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ |
|||
|
|||
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ |
|||
|
|||
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ |
|||
|
|||
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ |
|||
|
|||
uint32_t HashBuffSize; /*!< Size of buffer to be processed */ |
|||
|
|||
__IO uint32_t HashInCount; /*!< Counter of inputted data */ |
|||
|
|||
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */ |
|||
|
|||
__IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */ |
|||
|
|||
HAL_StatusTypeDef Status; /*!< HASH peripheral status */ |
|||
|
|||
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */ |
|||
|
|||
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */ |
|||
|
|||
HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ |
|||
|
|||
FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */ |
|||
|
|||
__IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< HASH Error code */ |
|||
|
|||
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ |
|||
|
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) |
|||
void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */ |
|||
|
|||
void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */ |
|||
|
|||
void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */ |
|||
|
|||
void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */ |
|||
|
|||
void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */ |
|||
|
|||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ |
|||
} HASH_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) |
|||
/**
|
|||
* @brief HAL HASH Callback pointer definition |
|||
*/ |
|||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */ |
|||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup HASH_Exported_Constants HASH Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup HASH_Algo_Selection HASH algorithm selection
|
|||
* @{ |
|||
*/ |
|||
#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */ |
|||
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ |
|||
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ |
|||
#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
|
|||
* @{ |
|||
*/ |
|||
#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */ |
|||
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HASH_Data_Type HASH input data type
|
|||
* @{ |
|||
*/ |
|||
#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */ |
|||
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ |
|||
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ |
|||
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
|
|||
* @{ |
|||
*/ |
|||
#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */ |
|||
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HASH_flags_definition HASH flags definitions
|
|||
* @{ |
|||
*/ |
|||
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */ |
|||
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ |
|||
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ |
|||
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ |
|||
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HASH_interrupts_definition HASH interrupts definitions
|
|||
* @{ |
|||
*/ |
|||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ |
|||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HASH_Error_Definition HASH Error Definition
|
|||
* @{ |
|||
*/ |
|||
#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */ |
|||
#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ |
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup HASH_Exported_Macros HASH Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Check whether or not the specified HASH flag is set.
|
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. |
|||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete. |
|||
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. |
|||
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. |
|||
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \ |
|||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ |
|||
((HASH->SR & (__FLAG__)) == (__FLAG__)) ) |
|||
|
|||
|
|||
/** @brief Clear the specified HASH flag.
|
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. |
|||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__)) |
|||
|
|||
|
|||
/** @brief Enable the specified HASH interrupt.
|
|||
* @param __INTERRUPT__ specifies the HASH interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) |
|||
* @arg @ref HASH_IT_DCI Digest calculation complete |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__)) |
|||
|
|||
/** @brief Disable the specified HASH interrupt.
|
|||
* @param __INTERRUPT__ specifies the HASH interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) |
|||
* @arg @ref HASH_IT_DCI Digest calculation complete |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__)) |
|||
|
|||
/** @brief Reset HASH handle state.
|
|||
* @param __HANDLE__ HASH handle. |
|||
* @retval None |
|||
*/ |
|||
|
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\ |
|||
(__HANDLE__)->State = HAL_HASH_STATE_RESET;\ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
}while(0) |
|||
#else |
|||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) |
|||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
/** @brief Reset HASH handle status.
|
|||
* @param __HANDLE__ HASH handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK) |
|||
|
|||
/**
|
|||
* @brief Enable the multi-buffer DMA transfer mode. |
|||
* @note This bit is set when hashing large files when multiple DMA transfers are needed. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) |
|||
|
|||
/**
|
|||
* @brief Disable the multi-buffer DMA transfer mode. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT) |
|||
|
|||
|
|||
/**
|
|||
* @brief Start the digest computation. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL) |
|||
|
|||
/**
|
|||
* @brief Set the number of valid bits in the last word written in data register DIN. |
|||
* @param __SIZE__ size in bytes of last data written in Data register. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) |
|||
|
|||
/**
|
|||
* @brief Reset the HASH core. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Private macros --------------------------------------------------------*/ |
|||
/** @defgroup HASH_Private_Macros HASH Private Macros
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief Return digest length in bytes. |
|||
* @retval Digest length |
|||
*/ |
|||
#if defined(HASH_CR_MDMAT) |
|||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \ |
|||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ |
|||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) |
|||
#else |
|||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : 16) |
|||
#endif /* HASH_CR_MDMAT*/ |
|||
/**
|
|||
* @brief Return number of words already pushed in the FIFO. |
|||
* @retval Number of words already pushed in the FIFO |
|||
*/ |
|||
#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U) |
|||
|
|||
/**
|
|||
* @brief Ensure that HASH input data type is valid. |
|||
* @param __DATATYPE__ HASH input data type. |
|||
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) |
|||
*/ |
|||
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \ |
|||
((__DATATYPE__) == HASH_DATATYPE_16B)|| \ |
|||
((__DATATYPE__) == HASH_DATATYPE_8B) || \ |
|||
((__DATATYPE__) == HASH_DATATYPE_1B)) |
|||
|
|||
/**
|
|||
* @brief Ensure that input data buffer size is valid for multi-buffer HASH |
|||
* processing in DMA mode. |
|||
* @note This check is valid only for multi-buffer HASH processing in DMA mode. |
|||
* @param __SIZE__ input data buffer size. |
|||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) |
|||
*/ |
|||
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U)) |
|||
|
|||
/**
|
|||
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC |
|||
* processing in DMA mode. |
|||
* @note This check is valid only for multi-buffer HMAC processing in DMA mode. |
|||
* @param __HANDLE__ HASH handle. |
|||
* @param __SIZE__ input data buffer size. |
|||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) |
|||
*/ |
|||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\ |
|||
|| (((__SIZE__) % 4U) == 0U)) |
|||
/**
|
|||
* @brief Ensure that handle phase is set to HASH processing. |
|||
* @param __HANDLE__ HASH handle. |
|||
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing) |
|||
*/ |
|||
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS) |
|||
|
|||
/**
|
|||
* @brief Ensure that handle phase is set to HMAC processing. |
|||
* @param __HANDLE__ HASH handle. |
|||
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing) |
|||
*/ |
|||
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \ |
|||
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \ |
|||
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include HASH HAL Extended module */ |
|||
#include "stm32f4xx_hal_hash_ex.h" |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions HASH Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization methods **********************************/ |
|||
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash); |
|||
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash); |
|||
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash); |
|||
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); |
|||
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); |
|||
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); |
|||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, |
|||
pHASH_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
/* HASH processing using polling *********************************************/ |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* HASH processing using IT **************************************************/ |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* HASH processing using DMA *************************************************/ |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* HASH-MAC processing using polling *****************************************/ |
|||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Timeout); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* HASH-HMAC processing using DMA ********************************************/ |
|||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
/* Peripheral State methods **************************************************/ |
|||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); |
|||
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); |
|||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); |
|||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); |
|||
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); |
|||
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); |
|||
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions -----------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup HASH_Private_Functions HASH Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Private functions */ |
|||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Timeout, uint32_t Algorithm); |
|||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); |
|||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); |
|||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Algorithm); |
|||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); |
|||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Timeout, uint32_t Algorithm); |
|||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, |
|||
uint32_t Algorithm); |
|||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* HASH*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_HASH_H */ |
|||
|
|||
@ -0,0 +1,175 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_hash_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of HASH HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_HASH_EX_H |
|||
#define STM32F4xx_HAL_HASH_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (HASH) |
|||
/** @addtogroup HASHEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
|
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, |
|||
uint8_t *pOutBuffer); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* HASH*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_HASH_EX_H */ |
|||
|
|||
@ -0,0 +1,316 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_hcd.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of HCD HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_HCD_H |
|||
#define STM32F4xx_HAL_HCD_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_ll_usb.h" |
|||
|
|||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS) |
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup HCD HCD
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup HCD_Exported_Types HCD Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_HCD_STATE_RESET = 0x00, |
|||
HAL_HCD_STATE_READY = 0x01, |
|||
HAL_HCD_STATE_ERROR = 0x02, |
|||
HAL_HCD_STATE_BUSY = 0x03, |
|||
HAL_HCD_STATE_TIMEOUT = 0x04 |
|||
} HCD_StateTypeDef; |
|||
|
|||
typedef USB_OTG_GlobalTypeDef HCD_TypeDef; |
|||
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; |
|||
typedef USB_OTG_HCTypeDef HCD_HCTypeDef; |
|||
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; |
|||
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
|
|||
* @{ |
|||
*/ |
|||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) |
|||
typedef struct __HCD_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ |
|||
{ |
|||
HCD_TypeDef *Instance; /*!< Register base address */ |
|||
HCD_InitTypeDef Init; /*!< HCD required parameters */ |
|||
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ |
|||
HAL_LockTypeDef Lock; /*!< HCD peripheral status */ |
|||
__IO HCD_StateTypeDef State; /*!< HCD communication state */ |
|||
__IO uint32_t ErrorCode; /*!< HCD Error code */ |
|||
void *pData; /*!< Pointer Stack Handler */ |
|||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) |
|||
void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ |
|||
void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ |
|||
void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ |
|||
void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ |
|||
void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ |
|||
void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, |
|||
HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ |
|||
|
|||
void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ |
|||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ |
|||
} HCD_HandleTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup HCD_Speed HCD Speed
|
|||
* @{ |
|||
*/ |
|||
#define HCD_SPEED_HIGH USBH_HS_SPEED |
|||
#define HCD_SPEED_FULL USBH_FSLS_SPEED |
|||
#define HCD_SPEED_LOW USBH_FSLS_SPEED |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HCD_Device_Speed HCD Device Speed
|
|||
* @{ |
|||
*/ |
|||
#define HCD_DEVICE_SPEED_HIGH 0U |
|||
#define HCD_DEVICE_SPEED_FULL 1U |
|||
#define HCD_DEVICE_SPEED_LOW 2U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HCD_PHY_Module HCD PHY Module
|
|||
* @{ |
|||
*/ |
|||
#define HCD_PHY_ULPI 1U |
|||
#define HCD_PHY_EMBEDDED 2U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HCD_Error_Code_definition HCD Error Code definition
|
|||
* @brief HCD Error Code definition |
|||
* @{ |
|||
*/ |
|||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
|||
* @brief macros to handle interrupts and specific clock configurations |
|||
* @{ |
|||
*/ |
|||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) |
|||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) |
|||
|
|||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) |
|||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) |
|||
|
|||
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) |
|||
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) |
|||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) |
|||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) |
|||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); |
|||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); |
|||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, |
|||
uint8_t epnum, uint8_t dev_address, |
|||
uint8_t speed, uint8_t ep_type, uint16_t mps); |
|||
|
|||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); |
|||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); |
|||
|
|||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) |
|||
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
|
|||
* @brief HAL USB OTG HCD Callback ID enumeration definition |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ |
|||
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ |
|||
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ |
|||
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ |
|||
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ |
|||
|
|||
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ |
|||
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ |
|||
|
|||
} HAL_HCD_CallbackIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
|
|||
* @brief HAL USB OTG HCD Callback pointer definition |
|||
* @{ |
|||
*/ |
|||
|
|||
typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ |
|||
typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, |
|||
uint8_t epnum, |
|||
HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, |
|||
HAL_HCD_CallbackIDTypeDef CallbackID, |
|||
pHCD_CallbackTypeDef pCallback); |
|||
|
|||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, |
|||
HAL_HCD_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, |
|||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); |
|||
|
|||
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); |
|||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* I/O operation functions ***************************************************/ |
|||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, |
|||
uint8_t direction, uint8_t ep_type, |
|||
uint8_t token, uint8_t *pbuff, |
|||
uint16_t length, uint8_t do_ping); |
|||
|
|||
/* Non-Blocking mode: Interrupt */ |
|||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); |
|||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, |
|||
HCD_URBStateTypeDef urb_state); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Peripheral Control functions **********************************************/ |
|||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); |
|||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); |
|||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Peripheral State functions ************************************************/ |
|||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
|||
* @{ |
|||
*/ |
|||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); |
|||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); |
|||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); |
|||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); |
|||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); |
|||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_HCD_H */ |
|||
@ -0,0 +1,741 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2c.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of I2C HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_I2C_H |
|||
#define __STM32F4xx_HAL_I2C_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2C
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
|||
* @brief I2C Configuration Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
|||
This parameter must be set to a value lower than 400kHz */ |
|||
|
|||
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
|||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ |
|||
|
|||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
|||
This parameter can be a 7-bit or 10-bit address. */ |
|||
|
|||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
|||
This parameter can be a value of @ref I2C_addressing_mode */ |
|||
|
|||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
|||
This parameter can be a value of @ref I2C_dual_addressing_mode */ |
|||
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
|||
This parameter can be a 7-bit address. */ |
|||
|
|||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
|||
This parameter can be a value of @ref I2C_general_call_addressing_mode */ |
|||
|
|||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
|||
This parameter can be a value of @ref I2C_nostretch_mode */ |
|||
|
|||
} I2C_InitTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
|||
* @brief HAL State structure definition |
|||
* @note HAL I2C State value coding follow below described bitmap : |
|||
* b7-b6 Error information |
|||
* 00 : No Error |
|||
* 01 : Abort (Abort user request on going) |
|||
* 10 : Timeout |
|||
* 11 : Error |
|||
* b5 Peripheral initialization status |
|||
* 0 : Reset (Peripheral not initialized) |
|||
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) |
|||
* b4 (not used) |
|||
* x : Should be set to 0 |
|||
* b3 |
|||
* 0 : Ready or Busy (No Listen mode ongoing) |
|||
* 1 : Listen (Peripheral in Address Listen Mode) |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (Peripheral busy with some configuration or internal operations) |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ |
|||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ |
|||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ |
|||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
|||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ |
|||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
|||
process is ongoing */ |
|||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
|||
process is ongoing */ |
|||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ |
|||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ |
|||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ |
|||
|
|||
} HAL_I2C_StateTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
|||
* @brief HAL Mode structure definition |
|||
* @note HAL I2C Mode value coding follow below described bitmap :\n |
|||
* b7 (not used)\n |
|||
* x : Should be set to 0\n |
|||
* b6\n |
|||
* 0 : None\n |
|||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n |
|||
* b5\n |
|||
* 0 : None\n |
|||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n |
|||
* b4\n |
|||
* 0 : None\n |
|||
* 1 : Master (HAL I2C communication is in Master Mode)\n |
|||
* b3-b2-b1-b0 (not used)\n |
|||
* xxxx : Should be set to 0000 |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ |
|||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ |
|||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ |
|||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ |
|||
|
|||
} HAL_I2C_ModeTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
|||
* @brief I2C Error Code definition |
|||
* @{ |
|||
*/ |
|||
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ |
|||
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ |
|||
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ |
|||
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ |
|||
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
|||
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ |
|||
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ |
|||
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ |
|||
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
|||
* @brief I2C handle Structure definition |
|||
* @{ |
|||
*/ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
typedef struct __I2C_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
{ |
|||
I2C_TypeDef *Instance; /*!< I2C registers base address */ |
|||
|
|||
I2C_InitTypeDef Init; /*!< I2C communication parameters */ |
|||
|
|||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ |
|||
|
|||
uint16_t XferSize; /*!< I2C transfer size */ |
|||
|
|||
__IO uint16_t XferCount; /*!< I2C transfer counter */ |
|||
|
|||
__IO uint32_t XferOptions; /*!< I2C transfer options */ |
|||
|
|||
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
|
|||
context for internal usage */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< I2C locking object */ |
|||
|
|||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ |
|||
|
|||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< I2C Error code */ |
|||
|
|||
__IO uint32_t Devaddress; /*!< I2C Target device address */ |
|||
|
|||
__IO uint32_t Memaddress; /*!< I2C Target memory address */ |
|||
|
|||
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */ |
|||
|
|||
__IO uint32_t EventCount; /*!< I2C Event counter */ |
|||
|
|||
|
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ |
|||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ |
|||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ |
|||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ |
|||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ |
|||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ |
|||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ |
|||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ |
|||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ |
|||
|
|||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ |
|||
|
|||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
} I2C_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL I2C Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ |
|||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ |
|||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ |
|||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ |
|||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ |
|||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ |
|||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ |
|||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ |
|||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ |
|||
|
|||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ |
|||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ |
|||
|
|||
} HAL_I2C_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL I2C Callback pointer definition |
|||
*/ |
|||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ |
|||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ |
|||
|
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
|
|||
* @{ |
|||
*/ |
|||
#define I2C_DUTYCYCLE_2 0x00000000U |
|||
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_addressing_mode I2C addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U |
|||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define I2C_DUALADDRESS_DISABLE 0x00000000U |
|||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define I2C_GENERALCALL_DISABLE 0x00000000U |
|||
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_nostretch_mode I2C nostretch mode
|
|||
* @{ |
|||
*/ |
|||
#define I2C_NOSTRETCH_DISABLE 0x00000000U |
|||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
|
|||
* @{ |
|||
*/ |
|||
#define I2C_MEMADD_SIZE_8BIT 0x00000001U |
|||
#define I2C_MEMADD_SIZE_16BIT 0x00000010U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
|
|||
* @{ |
|||
*/ |
|||
#define I2C_DIRECTION_RECEIVE 0x00000000U |
|||
#define I2C_DIRECTION_TRANSMIT 0x00000001U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
|
|||
* @{ |
|||
*/ |
|||
#define I2C_FIRST_FRAME 0x00000001U |
|||
#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U |
|||
#define I2C_NEXT_FRAME 0x00000004U |
|||
#define I2C_FIRST_AND_LAST_FRAME 0x00000008U |
|||
#define I2C_LAST_FRAME_NO_STOP 0x00000010U |
|||
#define I2C_LAST_FRAME 0x00000020U |
|||
|
|||
/* List of XferOptions in usage of :
|
|||
* 1- Restart condition in all use cases (direction change or not) |
|||
*/ |
|||
#define I2C_OTHER_FRAME (0x00AA0000U) |
|||
#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
|||
* @brief I2C Interrupt definition |
|||
* Elements values convention: 0xXXXXXXXX |
|||
* - XXXXXXXX : Interrupt control mask |
|||
* @{ |
|||
*/ |
|||
#define I2C_IT_BUF I2C_CR2_ITBUFEN |
|||
#define I2C_IT_EVT I2C_CR2_ITEVTEN |
|||
#define I2C_IT_ERR I2C_CR2_ITERREN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define I2C_FLAG_OVR 0x00010800U |
|||
#define I2C_FLAG_AF 0x00010400U |
|||
#define I2C_FLAG_ARLO 0x00010200U |
|||
#define I2C_FLAG_BERR 0x00010100U |
|||
#define I2C_FLAG_TXE 0x00010080U |
|||
#define I2C_FLAG_RXNE 0x00010040U |
|||
#define I2C_FLAG_STOPF 0x00010010U |
|||
#define I2C_FLAG_ADD10 0x00010008U |
|||
#define I2C_FLAG_BTF 0x00010004U |
|||
#define I2C_FLAG_ADDR 0x00010002U |
|||
#define I2C_FLAG_SB 0x00010001U |
|||
#define I2C_FLAG_DUALF 0x00100080U |
|||
#define I2C_FLAG_GENCALL 0x00100010U |
|||
#define I2C_FLAG_TRA 0x00100004U |
|||
#define I2C_FLAG_BUSY 0x00100002U |
|||
#define I2C_FLAG_MSL 0x00100001U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
|
|||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset I2C handle state.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) |
|||
#endif |
|||
|
|||
/** @brief Enable or disable the specified I2C interrupts.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2C_IT_BUF: Buffer interrupt enable |
|||
* @arg I2C_IT_EVT: Event interrupt enable |
|||
* @arg I2C_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) |
|||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
|||
|
|||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __INTERRUPT__ specifies the I2C interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2C_IT_BUF: Buffer interrupt enable |
|||
* @arg I2C_IT_EVT: Event interrupt enable |
|||
* @arg I2C_IT_ERR: Error interrupt enable |
|||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks whether the specified I2C flag is set or not.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag |
|||
* @arg I2C_FLAG_AF: Acknowledge failure flag |
|||
* @arg I2C_FLAG_ARLO: Arbitration lost flag |
|||
* @arg I2C_FLAG_BERR: Bus error flag |
|||
* @arg I2C_FLAG_TXE: Data register empty flag |
|||
* @arg I2C_FLAG_RXNE: Data register not empty flag |
|||
* @arg I2C_FLAG_STOPF: Stop detection flag |
|||
* @arg I2C_FLAG_ADD10: 10-bit header sent flag |
|||
* @arg I2C_FLAG_BTF: Byte transfer finished flag |
|||
* @arg I2C_FLAG_ADDR: Address sent flag |
|||
* Address matched flag |
|||
* @arg I2C_FLAG_SB: Start bit flag |
|||
* @arg I2C_FLAG_DUALF: Dual flag |
|||
* @arg I2C_FLAG_GENCALL: General call header flag |
|||
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag |
|||
* @arg I2C_FLAG_BUSY: Bus busy flag |
|||
* @arg I2C_FLAG_MSL: Master/Slave flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \ |
|||
(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \ |
|||
(((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)) |
|||
|
|||
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) |
|||
* @arg I2C_FLAG_AF: Acknowledge failure flag |
|||
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) |
|||
* @arg I2C_FLAG_BERR: Bus error flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) |
|||
|
|||
/** @brief Clears the I2C ADDR pending flag.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR1; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR2; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0) |
|||
|
|||
/** @brief Clears the I2C STOPF pending flag.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR1; \ |
|||
SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0) |
|||
|
|||
/** @brief Enable the specified I2C peripheral.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) |
|||
|
|||
/** @brief Disable the specified I2C peripheral.
|
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include I2C HAL Extension module */ |
|||
#include "stm32f4xx_hal_i2c_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup I2C_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions******************************/ |
|||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); |
|||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); |
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions ****************************************************/ |
|||
/******* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
|||
|
|||
/******* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); |
|||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); |
|||
|
|||
/******* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|||
* @{ |
|||
*/ |
|||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
|||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State, Mode and Error functions *********************************/ |
|||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); |
|||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); |
|||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define I2C_FLAG_MASK 0x0000FFFFU |
|||
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */ |
|||
#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) |
|||
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) |
|||
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) |
|||
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) |
|||
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) |
|||
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) |
|||
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ |
|||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ |
|||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) |
|||
|
|||
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0))) |
|||
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) |
|||
|
|||
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) |
|||
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) |
|||
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) |
|||
|
|||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) |
|||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) |
|||
|
|||
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
|
|||
* @{ |
|||
*/ |
|||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ |
|||
((CYCLE) == I2C_DUTYCYCLE_16_9)) |
|||
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ |
|||
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) |
|||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ |
|||
((ADDRESS) == I2C_DUALADDRESS_ENABLE)) |
|||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ |
|||
((CALL) == I2C_GENERALCALL_ENABLE)) |
|||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ |
|||
((STRETCH) == I2C_NOSTRETCH_ENABLE)) |
|||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ |
|||
((SIZE) == I2C_MEMADD_SIZE_16BIT)) |
|||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) |
|||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) |
|||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) |
|||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ |
|||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ |
|||
((REQUEST) == I2C_NEXT_FRAME) || \ |
|||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ |
|||
((REQUEST) == I2C_LAST_FRAME) || \ |
|||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ |
|||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) |
|||
|
|||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ |
|||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) |
|||
|
|||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) |
|||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* __STM32F4xx_HAL_I2C_H */ |
|||
|
|||
@ -0,0 +1,115 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2c_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of I2C HAL Extension module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_I2C_EX_H |
|||
#define __STM32F4xx_HAL_I2C_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2CEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Exported_Constants I2C Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2CEx_Analog_Filter I2C Analog Filter
|
|||
* @{ |
|||
*/ |
|||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U |
|||
#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup I2CEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2CEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ************************************************/ |
|||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); |
|||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Private_Constants I2C Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Private_Macros I2C Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ |
|||
((FILTER) == I2C_ANALOGFILTER_DISABLE)) |
|||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_I2C_EX_H */ |
|||
|
|||
|
|||
@ -0,0 +1,618 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2s.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of I2S HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_I2S_H |
|||
#define STM32F4xx_HAL_I2S_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2S
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief I2S Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
|||
This parameter can be a value of @ref I2S_Mode */ |
|||
|
|||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
|||
This parameter can be a value of @ref I2S_Standard */ |
|||
|
|||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
|||
This parameter can be a value of @ref I2S_Data_Format */ |
|||
|
|||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
|||
This parameter can be a value of @ref I2S_MCLK_Output */ |
|||
|
|||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
|||
This parameter can be a value of @ref I2S_Audio_Frequency */ |
|||
|
|||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
|||
This parameter can be a value of @ref I2S_Clock_Polarity */ |
|||
|
|||
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
|
|||
This parameter can be a value of @ref I2S_Clock_Source */ |
|||
uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
|
|||
This parameter can be a value of @ref I2S_FullDuplex_Mode */ |
|||
} I2S_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ |
|||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ |
|||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ |
|||
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
|||
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
|||
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
|||
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ |
|||
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ |
|||
} HAL_I2S_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief I2S handle Structure definition |
|||
*/ |
|||
typedef struct __I2S_HandleTypeDef |
|||
{ |
|||
SPI_TypeDef *Instance; /*!< I2S registers base address */ |
|||
|
|||
I2S_InitTypeDef Init; /*!< I2S communication parameters */ |
|||
|
|||
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ |
|||
|
|||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ |
|||
|
|||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ |
|||
|
|||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ |
|||
|
|||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
|||
(This field is initialized at the |
|||
same value as transfer size at the |
|||
beginning of the transfer and |
|||
decremented when a sample is received |
|||
NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
|||
void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ |
|||
|
|||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */ |
|||
|
|||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
|||
This parameter can be a value of @ref I2S_Error */ |
|||
|
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
|||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ |
|||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ |
|||
void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */ |
|||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ |
|||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ |
|||
void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */ |
|||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ |
|||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
|||
} I2S_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
|||
/**
|
|||
* @brief HAL I2S Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ |
|||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ |
|||
HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */ |
|||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ |
|||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ |
|||
HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */ |
|||
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ |
|||
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ |
|||
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ |
|||
|
|||
} HAL_I2S_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL I2S Callback pointer definition |
|||
*/ |
|||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ |
|||
|
|||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
|||
* @{ |
|||
*/ |
|||
/** @defgroup I2S_Error I2S Error
|
|||
* @{ |
|||
*/ |
|||
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ |
|||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ |
|||
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ |
|||
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ |
|||
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ |
|||
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ |
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
|||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Mode I2S Mode
|
|||
* @{ |
|||
*/ |
|||
#define I2S_MODE_SLAVE_TX (0x00000000U) |
|||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) |
|||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) |
|||
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Standard I2S Standard
|
|||
* @{ |
|||
*/ |
|||
#define I2S_STANDARD_PHILIPS (0x00000000U) |
|||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) |
|||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) |
|||
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) |
|||
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Data_Format I2S Data Format
|
|||
* @{ |
|||
*/ |
|||
#define I2S_DATAFORMAT_16B (0x00000000U) |
|||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) |
|||
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) |
|||
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
|||
* @{ |
|||
*/ |
|||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) |
|||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
|||
* @{ |
|||
*/ |
|||
#define I2S_AUDIOFREQ_192K (192000U) |
|||
#define I2S_AUDIOFREQ_96K (96000U) |
|||
#define I2S_AUDIOFREQ_48K (48000U) |
|||
#define I2S_AUDIOFREQ_44K (44100U) |
|||
#define I2S_AUDIOFREQ_32K (32000U) |
|||
#define I2S_AUDIOFREQ_22K (22050U) |
|||
#define I2S_AUDIOFREQ_16K (16000U) |
|||
#define I2S_AUDIOFREQ_11K (11025U) |
|||
#define I2S_AUDIOFREQ_8K (8000U) |
|||
#define I2S_AUDIOFREQ_DEFAULT (2U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
|
|||
* @{ |
|||
*/ |
|||
#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U) |
|||
#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
|||
* @{ |
|||
*/ |
|||
#define I2S_CPOL_LOW (0x00000000U) |
|||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
|||
* @{ |
|||
*/ |
|||
#define I2S_IT_TXE SPI_CR2_TXEIE |
|||
#define I2S_IT_RXNE SPI_CR2_RXNEIE |
|||
#define I2S_IT_ERR SPI_CR2_ERRIE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
|||
* @{ |
|||
*/ |
|||
#define I2S_FLAG_TXE SPI_SR_TXE |
|||
#define I2S_FLAG_RXNE SPI_SR_RXNE |
|||
|
|||
#define I2S_FLAG_UDR SPI_SR_UDR |
|||
#define I2S_FLAG_OVR SPI_SR_OVR |
|||
#define I2S_FLAG_FRE SPI_SR_FRE |
|||
|
|||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE |
|||
#define I2S_FLAG_BSY SPI_SR_BSY |
|||
|
|||
#define I2S_FLAG_MASK (SPI_SR_RXNE\ |
|||
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2S_Clock_Source I2S Clock Source Definition
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define I2S_CLOCK_PLL (0x00000000U) |
|||
#define I2S_CLOCK_EXTERNAL (0x00000001U) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || |
|||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ |
|||
|
|||
#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
|||
#define I2S_CLOCK_PLL (0x00000000U) |
|||
#define I2S_CLOCK_EXTERNAL (0x00000001U) |
|||
#define I2S_CLOCK_PLLR (0x00000002U) |
|||
#define I2S_CLOCK_PLLSRC (0x00000003U) |
|||
#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
|||
|
|||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) |
|||
#define I2S_CLOCK_PLLSRC (0x00000000U) |
|||
#define I2S_CLOCK_EXTERNAL (0x00000001U) |
|||
#define I2S_CLOCK_PLLR (0x00000002U) |
|||
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset I2S handle state
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
|||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) |
|||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
|||
|
|||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
|||
|
|||
/** @brief Enable the specified I2S interrupts.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg I2S_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) |
|||
|
|||
/** @brief Disable the specified I2S interrupts.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg I2S_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) |
|||
|
|||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. |
|||
* @param __INTERRUPT__ specifies the I2S interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg I2S_IT_ERR: Error interrupt enable |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks whether the specified I2S flag is set or not.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
|||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag |
|||
* @arg I2S_FLAG_UDR: Underrun flag |
|||
* @arg I2S_FLAG_OVR: Overrun flag |
|||
* @arg I2S_FLAG_FRE: Frame error flag |
|||
* @arg I2S_FLAG_CHSIDE: Channel Side flag |
|||
* @arg I2S_FLAG_BSY: Busy flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clears the I2S OVR pending flag.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ |
|||
__IO uint32_t tmpreg_ovr = 0x00U; \ |
|||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
|||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
|||
UNUSED(tmpreg_ovr); \ |
|||
}while(0U) |
|||
/** @brief Clears the I2S UDR pending flag.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ |
|||
__IO uint32_t tmpreg_udr = 0x00U;\ |
|||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\ |
|||
UNUSED(tmpreg_udr); \ |
|||
}while(0U) |
|||
/** @brief Flush the I2S DR Register.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ |
|||
__IO uint32_t tmpreg_dr = 0x00U;\ |
|||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\ |
|||
UNUSED(tmpreg_dr); \ |
|||
}while(0U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include I2S Extension module */ |
|||
#include "stm32f4xx_hal_i2s_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup I2S_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2S_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); |
|||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
|||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, |
|||
pI2S_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2S_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ***************************************************/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
|||
|
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
|||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); |
|||
|
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); |
|||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); |
|||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); |
|||
|
|||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
|||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2S_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control and State functions ************************************/ |
|||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); |
|||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Check whether the specified SPI flag is set or not.
|
|||
* @param __SR__ copy of I2S SR register. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
|||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag |
|||
* @arg I2S_FLAG_UDR: Underrun error flag |
|||
* @arg I2S_FLAG_OVR: Overrun flag |
|||
* @arg I2S_FLAG_CHSIDE: Channel side flag |
|||
* @arg I2S_FLAG_BSY: Busy flag |
|||
* @retval SET or RESET. |
|||
*/ |
|||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ |
|||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) |
|||
|
|||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
|||
* @param __CR2__ copy of I2S CR2 register. |
|||
* @param __INTERRUPT__ specifies the SPI interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg I2S_IT_ERR: Error interrupt enable |
|||
* @retval SET or RESET. |
|||
*/ |
|||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
|||
* @param __MODE__ specifies the I2S Mode. |
|||
* This parameter can be a value of @ref I2S_Mode |
|||
* @retval None |
|||
*/ |
|||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ |
|||
((__MODE__) == I2S_MODE_SLAVE_RX) || \ |
|||
((__MODE__) == I2S_MODE_MASTER_TX) || \ |
|||
((__MODE__) == I2S_MODE_MASTER_RX)) |
|||
|
|||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ |
|||
((__STANDARD__) == I2S_STANDARD_MSB) || \ |
|||
((__STANDARD__) == I2S_STANDARD_LSB) || \ |
|||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ |
|||
((__STANDARD__) == I2S_STANDARD_PCM_LONG)) |
|||
|
|||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ |
|||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ |
|||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \ |
|||
((__FORMAT__) == I2S_DATAFORMAT_32B)) |
|||
|
|||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ |
|||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) |
|||
|
|||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ |
|||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ |
|||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) |
|||
|
|||
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \ |
|||
((MODE) == I2S_FULLDUPLEXMODE_ENABLE)) |
|||
|
|||
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
|
|||
* @param __CPOL__ specifies the I2S serial clock steady state. |
|||
* This parameter can be a value of @ref I2S_Clock_Polarity |
|||
* @retval None |
|||
*/ |
|||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ |
|||
((__CPOL__) == I2S_CPOL_HIGH)) |
|||
|
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ |
|||
((CLOCK) == I2S_CLOCK_PLL)) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || |
|||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ |
|||
|
|||
#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) || defined(STM32F423xx) |
|||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ |
|||
((CLOCK) == I2S_CLOCK_PLL) ||\ |
|||
((CLOCK) == I2S_CLOCK_PLLSRC) ||\ |
|||
((CLOCK) == I2S_CLOCK_PLLR)) |
|||
#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
|||
|
|||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) |
|||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ |
|||
((CLOCK) == I2S_CLOCK_PLLSRC) ||\ |
|||
((CLOCK) == I2S_CLOCK_PLLR)) |
|||
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_I2S_H */ |
|||
|
|||
@ -0,0 +1,183 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2s_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of I2S HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_I2S_EX_H |
|||
#define STM32F4xx_HAL_I2S_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT) |
|||
/** @addtogroup I2SEx I2SEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) |
|||
|
|||
/** @brief Enable or disable the specified I2SExt peripheral.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE) |
|||
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE) |
|||
|
|||
/** @brief Enable or disable the specified I2SExt interrupts.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg I2S_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__)) |
|||
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__)) |
|||
|
|||
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. |
|||
* @param __INTERRUPT__ specifies the I2S interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg I2S_IT_ERR: Error interrupt enable |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks whether the specified I2SExt flag is set or not.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
|||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag |
|||
* @arg I2S_FLAG_UDR: Underrun flag |
|||
* @arg I2S_FLAG_OVR: Overrun flag |
|||
* @arg I2S_FLAG_FRE: Frame error flag |
|||
* @arg I2S_FLAG_CHSIDE: Channel Side flag |
|||
* @arg I2S_FLAG_BSY: Busy flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clears the I2SExt OVR pending flag.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \ |
|||
__IO uint32_t tmpreg_ovr = 0x00U; \ |
|||
tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\ |
|||
tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\ |
|||
UNUSED(tmpreg_ovr); \ |
|||
}while(0U) |
|||
/** @brief Clears the I2SExt UDR pending flag.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \ |
|||
__IO uint32_t tmpreg_udr = 0x00U; \ |
|||
tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\ |
|||
UNUSED(tmpreg_udr); \ |
|||
}while(0U) |
|||
/** @brief Flush the I2S and I2SExt DR Registers.
|
|||
* @param __HANDLE__ specifies the I2S Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \ |
|||
__IO uint32_t tmpreg_dr = 0x00U; \ |
|||
tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \ |
|||
tmpreg_dr = ((__HANDLE__)->Instance->DR); \ |
|||
UNUSED(tmpreg_dr); \ |
|||
}while(0U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Extended features functions *************************************************/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, |
|||
uint16_t Size, uint32_t Timeout); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, |
|||
uint16_t Size); |
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, |
|||
uint16_t Size); |
|||
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
|||
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
|||
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_I2S_EX_H */ |
|||
|
|||
@ -0,0 +1,682 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_irda.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of IRDA HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_IRDA_H |
|||
#define __STM32F4xx_HAL_IRDA_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup IRDA
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief IRDA Init Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
|||
The baud rate is computed using the following formula: |
|||
- IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate))) |
|||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ |
|||
|
|||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
|||
This parameter can be a value of @ref IRDA_Word_Length */ |
|||
|
|||
uint32_t Parity; /*!< Specifies the parity mode.
|
|||
This parameter can be a value of @ref IRDA_Parity |
|||
@note When parity is enabled, the computed parity is inserted |
|||
at the MSB position of the transmitted data (9th bit when |
|||
the word length is set to 9 data bits; 8th bit when the |
|||
word length is set to 8 data bits). */ |
|||
|
|||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
|||
This parameter can be a value of @ref IRDA_Mode */ |
|||
|
|||
uint8_t Prescaler; /*!< Specifies the Prescaler value to be programmed
|
|||
in the IrDA low-power Baud Register, for defining pulse width on which |
|||
burst acceptance/rejection will be decided. This value is used as divisor |
|||
of system clock to achieve required pulse width. */ |
|||
|
|||
uint32_t IrDAMode; /*!< Specifies the IrDA mode
|
|||
This parameter can be a value of @ref IRDA_Low_Power */ |
|||
} IRDA_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL IRDA State structures definition |
|||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. |
|||
* - gState contains IRDA state information related to global Handle management |
|||
* and also information related to Tx operations. |
|||
* gState value coding follow below described bitmap : |
|||
* b7-b6 Error information |
|||
* 00 : No Error |
|||
* 01 : (Not Used) |
|||
* 10 : Timeout |
|||
* 11 : Error |
|||
* b5 IP initialisation status |
|||
* 0 : Reset (IP not initialized) |
|||
* 1 : Init done (IP initialized. HAL IRDA Init function already called) |
|||
* b4-b3 (not used) |
|||
* xx : Should be set to 00 |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (IP busy with some configuration or internal operations) |
|||
* b1 (not used) |
|||
* x : Should be set to 0 |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* - RxState contains information related to Rx operations. |
|||
* RxState value coding follow below described bitmap : |
|||
* b7-b6 (not used) |
|||
* xx : Should be set to 00 |
|||
* b5 IP initialisation status |
|||
* 0 : Reset (IP not initialized) |
|||
* 1 : Init done (IP initialized) |
|||
* b4-b2 (not used) |
|||
* xxx : Should be set to 000 |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 (not used) |
|||
* x : Should be set to 0. |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
|||
Value is allowed for gState and RxState */ |
|||
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
|||
Value is allowed for gState and RxState */ |
|||
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
|
|||
Value is allowed for gState only */ |
|||
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
|||
Value is allowed for gState only */ |
|||
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
|||
Value is allowed for RxState only */ |
|||
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
|||
Not to be used for neither gState nor RxState. |
|||
Value is result of combination (Or) between gState and RxState values */ |
|||
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
|||
Value is allowed for gState only */ |
|||
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
|
|||
Value is allowed for gState only */ |
|||
} HAL_IRDA_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief IRDA handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) |
|||
typedef struct __IRDA_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ |
|||
{ |
|||
USART_TypeDef *Instance; /*!< USART registers base address */ |
|||
|
|||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ |
|||
|
|||
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ |
|||
|
|||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ |
|||
|
|||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ |
|||
|
|||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
|||
and also related to Tx operations. |
|||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ |
|||
|
|||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
|||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< IRDA Error code */ |
|||
|
|||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) |
|||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ |
|||
|
|||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */ |
|||
|
|||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */ |
|||
|
|||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */ |
|||
|
|||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */ |
|||
|
|||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */ |
|||
|
|||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */ |
|||
|
|||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */ |
|||
|
|||
|
|||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */ |
|||
|
|||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */ |
|||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ |
|||
|
|||
} IRDA_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL IRDA Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */ |
|||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */ |
|||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */ |
|||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */ |
|||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */ |
|||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */ |
|||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */ |
|||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */ |
|||
|
|||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */ |
|||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */ |
|||
|
|||
} HAL_IRDA_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL IRDA Callback pointer definition |
|||
*/ |
|||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */ |
|||
|
|||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
|
|||
* @{ |
|||
*/ |
|||
/** @defgroup IRDA_Error_Code IRDA Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */ |
|||
#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */ |
|||
#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */ |
|||
#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */ |
|||
#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
|||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) |
|||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IRDA_Word_Length IRDA Word Length
|
|||
* @{ |
|||
*/ |
|||
#define IRDA_WORDLENGTH_8B 0x00000000U |
|||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IRDA_Parity IRDA Parity
|
|||
* @{ |
|||
*/ |
|||
#define IRDA_PARITY_NONE 0x00000000U |
|||
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) |
|||
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IRDA_Mode IRDA Transfer Mode
|
|||
* @{ |
|||
*/ |
|||
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) |
|||
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) |
|||
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
|||
* @{ |
|||
*/ |
|||
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) |
|||
#define IRDA_POWERMODE_NORMAL 0x00000000U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IRDA_Flags IRDA Flags
|
|||
* Elements values convention: 0xXXXX |
|||
* - 0xXXXX : Flag mask in the SR register |
|||
* @{ |
|||
*/ |
|||
#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE) |
|||
#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC) |
|||
#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE) |
|||
#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE) |
|||
#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE) |
|||
#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE) |
|||
#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE) |
|||
#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
|
|||
* Elements values convention: 0xY000XXXX |
|||
* - XXXX : Interrupt mask in the XX register |
|||
* - Y : Interrupt source register (2bits) |
|||
* - 01: CR1 register |
|||
* - 10: CR2 register |
|||
* - 11: CR3 register |
|||
* @{ |
|||
*/ |
|||
#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) |
|||
#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) |
|||
#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) |
|||
#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) |
|||
#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) |
|||
|
|||
#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) |
|||
|
|||
#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) |
|||
#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset IRDA handle gstate & RxState
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 |
|||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0U) |
|||
#else |
|||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ |
|||
} while(0U) |
|||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Flush the IRDA DR register
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) |
|||
|
|||
/** @brief Check whether the specified IRDA flag is set or not.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg IRDA_FLAG_TXE: Transmit data register empty flag |
|||
* @arg IRDA_FLAG_TC: Transmission Complete flag |
|||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag |
|||
* @arg IRDA_FLAG_IDLE: Idle Line detection flag |
|||
* @arg IRDA_FLAG_ORE: OverRun Error flag |
|||
* @arg IRDA_FLAG_NE: Noise Error flag |
|||
* @arg IRDA_FLAG_FE: Framing Error flag |
|||
* @arg IRDA_FLAG_PE: Parity Error flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clear the specified IRDA pending flag.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg IRDA_FLAG_TC: Transmission Complete flag. |
|||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag. |
|||
* |
|||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun |
|||
* error) and IDLE (Idle line detected) flags are cleared by software |
|||
* sequence: a read operation to USART_SR register followed by a read |
|||
* operation to USART_DR register. |
|||
* @note RXNE flag can be also cleared by a read to the USART_DR register. |
|||
* @note TC flag can be also cleared by software sequence: a read operation to |
|||
* USART_SR register followed by a write operation to USART_DR register. |
|||
* @note TXE flag is cleared only by a write to the USART_DR register. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
|||
|
|||
/** @brief Clear the IRDA PE pending flag.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR; \ |
|||
tmpreg = (__HANDLE__)->Instance->DR; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Clear the IRDA FE pending flag.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the IRDA NE pending flag.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the IRDA ORE pending flag.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the IRDA IDLE pending flag.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Enable the specified IRDA interrupt.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg IRDA_IT_TC: Transmission complete interrupt |
|||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg IRDA_IT_IDLE: Idle line detection interrupt |
|||
* @arg IRDA_IT_PE: Parity Error interrupt |
|||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ |
|||
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK))) |
|||
/** @brief Disable the specified IRDA interrupt.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg IRDA_IT_TC: Transmission complete interrupt |
|||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg IRDA_IT_IDLE: Idle line detection interrupt |
|||
* @arg IRDA_IT_PE: Parity Error interrupt |
|||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ |
|||
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) |
|||
|
|||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __IT__ specifies the IRDA interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg IRDA_IT_TC: Transmission complete interrupt |
|||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg IRDA_IT_IDLE: Idle line detection interrupt |
|||
* @arg IRDA_IT_ERR: Error interrupt |
|||
* @arg IRDA_IT_PE: Parity Error interrupt |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \ |
|||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK)) |
|||
|
|||
/** @brief Macro to enable the IRDA's one bit sample method
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT) |
|||
|
|||
/** @brief Macro to disable the IRDA's one bit sample method
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) |
|||
|
|||
/** @brief Enable UART/USART associated to IRDA Handle
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) |
|||
|
|||
/** @brief Disable UART/USART associated to IRDA Handle
|
|||
* @param __HANDLE__ specifies the IRDA Handle. |
|||
* IRDA Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup IRDA_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup IRDA_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); |
|||
|
|||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup IRDA_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *******************************************************/ |
|||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); |
|||
/* Transfer Abort functions */ |
|||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda); |
|||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda); |
|||
|
|||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup IRDA_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions **************************************************/ |
|||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); |
|||
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup IRDA_Private_Constants IRDA Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief IRDA interruptions flag mask
|
|||
* |
|||
*/ |
|||
#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ |
|||
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) |
|||
|
|||
#define IRDA_CR1_REG_INDEX 1U |
|||
#define IRDA_CR2_REG_INDEX 2U |
|||
#define IRDA_CR3_REG_INDEX 3U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros --------------------------------------------------------*/ |
|||
/** @defgroup IRDA_Private_Macros IRDA Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ |
|||
((LENGTH) == IRDA_WORDLENGTH_9B)) |
|||
|
|||
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ |
|||
((PARITY) == IRDA_PARITY_EVEN) || \ |
|||
((PARITY) == IRDA_PARITY_ODD)) |
|||
|
|||
#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U)) |
|||
|
|||
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ |
|||
((MODE) == IRDA_POWERMODE_NORMAL)) |
|||
|
|||
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U) |
|||
|
|||
#define IRDA_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*(((uint64_t)(_BAUD_)))))) |
|||
|
|||
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U) |
|||
|
|||
#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) |
|||
|
|||
/* UART BRR = mantissa + overflow + fraction
|
|||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ |
|||
#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \ |
|||
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \ |
|||
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup IRDA_Private_Functions IRDA Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_IRDA_H */ |
|||
|
|||
@ -0,0 +1,220 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_iwdg.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of IWDG HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_IWDG_H |
|||
#define STM32F4xx_HAL_IWDG_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup IWDG IWDG
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief IWDG Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
|||
This parameter can be a value of @ref IWDG_Prescaler */ |
|||
|
|||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ |
|||
|
|||
} IWDG_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief IWDG Handle Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
IWDG_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */ |
|||
} IWDG_HandleTypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ |
|||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ |
|||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ |
|||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ |
|||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ |
|||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ |
|||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Enable the IWDG peripheral. |
|||
* @param __HANDLE__ IWDG handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) |
|||
|
|||
/**
|
|||
* @brief Reload IWDG counter with value defined in the reload register |
|||
* (write access to IWDG_PR and IWDG_RLR registers disabled). |
|||
* @param __HANDLE__ IWDG handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/Start functions ********************************************/ |
|||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ****************************************************/ |
|||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief IWDG Key Register BitMask |
|||
*/ |
|||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ |
|||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ |
|||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ |
|||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Enable write access to IWDG_PR and IWDG_RLR registers. |
|||
* @param __HANDLE__ IWDG handle |
|||
* @retval None |
|||
*/ |
|||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) |
|||
|
|||
/**
|
|||
* @brief Disable write access to IWDG_PR and IWDG_RLR registers. |
|||
* @param __HANDLE__ IWDG handle |
|||
* @retval None |
|||
*/ |
|||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) |
|||
|
|||
/**
|
|||
* @brief Check IWDG prescaler value. |
|||
* @param __PRESCALER__ IWDG prescaler value |
|||
* @retval None |
|||
*/ |
|||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ |
|||
((__PRESCALER__) == IWDG_PRESCALER_8) || \ |
|||
((__PRESCALER__) == IWDG_PRESCALER_16) || \ |
|||
((__PRESCALER__) == IWDG_PRESCALER_32) || \ |
|||
((__PRESCALER__) == IWDG_PRESCALER_64) || \ |
|||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \ |
|||
((__PRESCALER__) == IWDG_PRESCALER_256)) |
|||
|
|||
/**
|
|||
* @brief Check IWDG reload value. |
|||
* @param __RELOAD__ IWDG reload value |
|||
* @retval None |
|||
*/ |
|||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) |
|||
|
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_IWDG_H */ |
|||
@ -0,0 +1,857 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_lptim.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of LPTIM HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_LPTIM_H |
|||
#define STM32F4xx_HAL_LPTIM_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (LPTIM1) |
|||
|
|||
/** @addtogroup LPTIM
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR23 /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */ |
|||
|
|||
/**
|
|||
* @brief LPTIM Clock configuration definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Source; /*!< Selects the clock source.
|
|||
This parameter can be a value of @ref LPTIM_Clock_Source */ |
|||
|
|||
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
|
|||
This parameter can be a value of @ref LPTIM_Clock_Prescaler */ |
|||
|
|||
} LPTIM_ClockConfigTypeDef; |
|||
|
|||
/**
|
|||
* @brief LPTIM Clock configuration definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
|
|||
if the ULPTIM input is selected. |
|||
Note: This parameter is used only when Ultra low power clock source is used. |
|||
Note: If the polarity is configured on 'both edges', an auxiliary clock |
|||
(one of the Low power oscillator) must be active. |
|||
This parameter can be a value of @ref LPTIM_Clock_Polarity */ |
|||
|
|||
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
|
|||
Note: This parameter is used only when Ultra low power clock source is used. |
|||
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ |
|||
|
|||
} LPTIM_ULPClockConfigTypeDef; |
|||
|
|||
/**
|
|||
* @brief LPTIM Trigger configuration definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Source; /*!< Selects the Trigger source.
|
|||
This parameter can be a value of @ref LPTIM_Trigger_Source */ |
|||
|
|||
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
|
|||
Note: This parameter is used only when an external trigger is used. |
|||
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ |
|||
|
|||
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
|
|||
Note: This parameter is used only when an external trigger is used. |
|||
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ |
|||
} LPTIM_TriggerConfigTypeDef; |
|||
|
|||
/**
|
|||
* @brief LPTIM Initialization Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ |
|||
|
|||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ |
|||
|
|||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ |
|||
|
|||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
|||
This parameter can be a value of @ref LPTIM_Output_Polarity */ |
|||
|
|||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
|||
values is done immediately or after the end of current period. |
|||
This parameter can be a value of @ref LPTIM_Updating_Mode */ |
|||
|
|||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
|||
or each external event. |
|||
This parameter can be a value of @ref LPTIM_Counter_Source */ |
|||
} LPTIM_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL LPTIM State structure definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
|||
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
|||
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
|||
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ |
|||
} HAL_LPTIM_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief LPTIM handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) |
|||
typedef struct __LPTIM_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ |
|||
{ |
|||
LPTIM_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ |
|||
|
|||
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< LPTIM locking object */ |
|||
|
|||
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ |
|||
|
|||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) |
|||
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ |
|||
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ |
|||
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ |
|||
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ |
|||
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ |
|||
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ |
|||
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ |
|||
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ |
|||
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ |
|||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ |
|||
} LPTIM_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL LPTIM Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ |
|||
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ |
|||
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ |
|||
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ |
|||
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ |
|||
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ |
|||
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ |
|||
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ |
|||
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ |
|||
} HAL_LPTIM_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL TIM Callback pointer definition |
|||
*/ |
|||
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ |
|||
|
|||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U |
|||
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_PRESCALER_DIV1 0x00000000U |
|||
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 |
|||
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 |
|||
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) |
|||
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 |
|||
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) |
|||
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) |
|||
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U |
|||
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U |
|||
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 |
|||
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 |
|||
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U |
|||
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 |
|||
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU |
|||
#define LPTIM_TRIGSOURCE_0 0x00000000U |
|||
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 |
|||
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 |
|||
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) |
|||
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 |
|||
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 |
|||
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 |
|||
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U |
|||
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 |
|||
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 |
|||
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U |
|||
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U |
|||
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN |
|||
#define LPTIM_FLAG_UP LPTIM_ISR_UP |
|||
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK |
|||
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK |
|||
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG |
|||
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM |
|||
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE |
|||
#define LPTIM_IT_UP LPTIM_IER_UPIE |
|||
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE |
|||
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE |
|||
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE |
|||
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE |
|||
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LPTIM_Option Register Definition
|
|||
* @{ |
|||
*/ |
|||
#define LPTIM_OP_PAD_AF 0x00000000U |
|||
#define LPTIM_OP_PAD_PA4 LPTIM_OR_LPT_IN1_RMP_0 |
|||
#define LPTIM_OP_PAD_PB9 LPTIM_OR_LPT_IN1_RMP_1 |
|||
#define LPTIM_OP_TIM_DAC LPTIM_OR_LPT_IN1_RMP |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset LPTIM handle state.
|
|||
* @param __HANDLE__ LPTIM handle |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) |
|||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable the LPTIM peripheral. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) |
|||
|
|||
/**
|
|||
* @brief Disable the LPTIM peripheral. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @note The following sequence is required to solve LPTIM disable HW limitation. |
|||
* Please check Errata Sheet ES0335 for more details under "MCU may remain |
|||
* stuck in LPTIM interrupt when entering Stop mode" section. |
|||
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to |
|||
* check for TIMEOUT. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) |
|||
|
|||
/**
|
|||
* @brief Start the LPTIM peripheral in Continuous mode. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) |
|||
/**
|
|||
* @brief Start the LPTIM peripheral in single mode. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) |
|||
|
|||
/**
|
|||
* @brief Write the passed parameter in the Autoreload register. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @param __VALUE__ Autoreload value |
|||
* @retval None |
|||
* @note The ARR register can only be modified when the LPTIM instance is enabled. |
|||
*/ |
|||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) |
|||
|
|||
/**
|
|||
* @brief Write the passed parameter in the Compare register. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @param __VALUE__ Compare value |
|||
* @retval None |
|||
* @note The CMP register can only be modified when the LPTIM instance is enabled. |
|||
*/ |
|||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified LPTIM flag is set or not. |
|||
* @param __HANDLE__ LPTIM handle |
|||
* @param __FLAG__ LPTIM flag to check |
|||
* This parameter can be a value of: |
|||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. |
|||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. |
|||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. |
|||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. |
|||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. |
|||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag. |
|||
* @arg LPTIM_FLAG_CMPM : Compare match Flag. |
|||
* @retval The state of the specified flag (SET or RESET). |
|||
*/ |
|||
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the specified LPTIM flag. |
|||
* @param __HANDLE__ LPTIM handle. |
|||
* @param __FLAG__ LPTIM flag to clear. |
|||
* This parameter can be a value of: |
|||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. |
|||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. |
|||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. |
|||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. |
|||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. |
|||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag. |
|||
* @arg LPTIM_FLAG_CMPM : Compare match Flag. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Enable the specified LPTIM interrupt. |
|||
* @param __HANDLE__ LPTIM handle. |
|||
* @param __INTERRUPT__ LPTIM interrupt to set. |
|||
* This parameter can be a value of: |
|||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. |
|||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. |
|||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. |
|||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. |
|||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. |
|||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt. |
|||
* @arg LPTIM_IT_CMPM : Compare match Interrupt. |
|||
* @retval None. |
|||
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. |
|||
*/ |
|||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the specified LPTIM interrupt. |
|||
* @param __HANDLE__ LPTIM handle. |
|||
* @param __INTERRUPT__ LPTIM interrupt to set. |
|||
* This parameter can be a value of: |
|||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. |
|||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. |
|||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. |
|||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. |
|||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. |
|||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt. |
|||
* @arg LPTIM_IT_CMPM : Compare match Interrupt. |
|||
* @retval None. |
|||
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. |
|||
*/ |
|||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified LPTIM interrupt source is enabled or not. |
|||
* @param __HANDLE__ LPTIM handle. |
|||
* @param __INTERRUPT__ LPTIM interrupt to check. |
|||
* This parameter can be a value of: |
|||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. |
|||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. |
|||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. |
|||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. |
|||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. |
|||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt. |
|||
* @arg LPTIM_IT_CMPM : Compare match Interrupt. |
|||
* @retval Interrupt status. |
|||
*/ |
|||
|
|||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief LPTIM Option Register
|
|||
* @param __HANDLE__ LPTIM handle |
|||
* @param __VALUE__ This parameter can be a value of : |
|||
* @arg LPTIM_OP_PAD_AF |
|||
* @arg LPTIM_OP_PAD_PA4 |
|||
* @arg LPTIM_OP_PAD_PB9 |
|||
* @arg LPTIM_OP_TIM_DAC |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__)) |
|||
|
|||
|
|||
/**
|
|||
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\ |
|||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\ |
|||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) |
|||
|
|||
/**
|
|||
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\ |
|||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\ |
|||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) |
|||
#if defined(EXTI_IMR_MR23) |
|||
|
|||
/**
|
|||
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\ |
|||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\ |
|||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) |
|||
|
|||
/**
|
|||
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\ |
|||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\ |
|||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) |
|||
|
|||
/**
|
|||
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\ |
|||
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\ |
|||
}while(0) |
|||
|
|||
/**
|
|||
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ |
|||
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ |
|||
}while(0) |
|||
|
|||
/**
|
|||
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not. |
|||
* @retval Line Status. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\ |
|||
& LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
|
|||
/**
|
|||
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\ |
|||
= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
|
|||
/**
|
|||
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\ |
|||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) |
|||
#endif /* EXTI_IMR_MR23 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
|||
* @brief Initialization and Configuration functions. |
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); |
|||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* MSP functions *************************************************************/ |
|||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
|||
* @brief Start-Stop operation functions. |
|||
* @{ |
|||
*/ |
|||
/* Start/Stop operation functions *********************************************/ |
|||
/* ################################# PWM Mode ################################*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); |
|||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); |
|||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* ############################# One Pulse Mode ##############################*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); |
|||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); |
|||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* ############################## Set once Mode ##############################*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); |
|||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); |
|||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* ############################### Encoder Mode ##############################*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period); |
|||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); |
|||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* ############################# Time out Mode ##############################*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* ############################## Counter Mode ###############################*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period); |
|||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); |
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); |
|||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
|||
* @brief Read operation functions. |
|||
* @{ |
|||
*/ |
|||
/* Reading operation functions ************************************************/ |
|||
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); |
|||
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); |
|||
uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
|||
* @brief LPTIM IRQ handler and callback functions. |
|||
* @{ |
|||
*/ |
|||
/* LPTIM IRQ functions *******************************************************/ |
|||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* CallBack functions ********************************************************/ |
|||
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); |
|||
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, |
|||
pLPTIM_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LPTIM_Group5
|
|||
* @brief Peripheral State functions. |
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ************************************************/ |
|||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ |
|||
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) |
|||
|
|||
|
|||
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ |
|||
((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) |
|||
|
|||
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) |
|||
|
|||
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \ |
|||
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) |
|||
|
|||
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ |
|||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ |
|||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ |
|||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) |
|||
|
|||
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ |
|||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ |
|||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) |
|||
|
|||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ |
|||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ |
|||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ |
|||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ |
|||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ |
|||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ |
|||
((__TRIG__) == LPTIM_TRIGSOURCE_5)) |
|||
|
|||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ |
|||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ |
|||
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) |
|||
|
|||
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ |
|||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ |
|||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ |
|||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) |
|||
|
|||
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ |
|||
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) |
|||
|
|||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ |
|||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) |
|||
|
|||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ |
|||
((__AUTORELOAD__) <= 0x0000FFFFUL)) |
|||
|
|||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) |
|||
|
|||
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ |
|||
((__PERIOD__) <= 0x0000FFFFUL)) |
|||
|
|||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
|||
* @{ |
|||
*/ |
|||
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* LPTIM1 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_LPTIM_H */ |
|||
@ -0,0 +1,719 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_ltdc.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of LTDC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_LTDC_H |
|||
#define STM32F4xx_HAL_LTDC_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
#if defined (LTDC) |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup LTDC LTDC
|
|||
* @brief LTDC HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup LTDC_Exported_Types LTDC Exported Types
|
|||
* @{ |
|||
*/ |
|||
#define MAX_LAYER 2U |
|||
|
|||
/**
|
|||
* @brief LTDC color structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint8_t Blue; /*!< Configures the blue value.
|
|||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
|||
|
|||
uint8_t Green; /*!< Configures the green value.
|
|||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
|||
|
|||
uint8_t Red; /*!< Configures the red value.
|
|||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
|||
|
|||
uint8_t Reserved; /*!< Reserved 0xFF */ |
|||
} LTDC_ColorTypeDef; |
|||
|
|||
/**
|
|||
* @brief LTDC Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
|
|||
This parameter can be one value of @ref LTDC_HS_POLARITY */ |
|||
|
|||
uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
|
|||
This parameter can be one value of @ref LTDC_VS_POLARITY */ |
|||
|
|||
uint32_t DEPolarity; /*!< configures the data enable polarity.
|
|||
This parameter can be one of value of @ref LTDC_DE_POLARITY */ |
|||
|
|||
uint32_t PCPolarity; /*!< configures the pixel clock polarity.
|
|||
This parameter can be one of value of @ref LTDC_PC_POLARITY */ |
|||
|
|||
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x000 and Max_Data = 0xFFF. */ |
|||
|
|||
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x000 and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
|
|||
This parameter must be a number between |
|||
Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ |
|||
|
|||
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
|
|||
This parameter must be a number between |
|||
Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
|
|||
This parameter must be a number between |
|||
Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ |
|||
|
|||
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
|
|||
This parameter must be a number between |
|||
Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t TotalWidth; /*!< configures the total width.
|
|||
This parameter must be a number between |
|||
Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ |
|||
|
|||
uint32_t TotalHeigh; /*!< configures the total height.
|
|||
This parameter must be a number between |
|||
Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ |
|||
|
|||
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ |
|||
} LTDC_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief LTDC Layer structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x000 and Max_Data = 0xFFF. */ |
|||
|
|||
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x000 and Max_Data = 0xFFF. */ |
|||
|
|||
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x000 and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0x7FF. */ |
|||
|
|||
uint32_t PixelFormat; /*!< Specifies the pixel format.
|
|||
This parameter can be one of value of @ref LTDC_Pixelformat */ |
|||
|
|||
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x00 and Max_Data = 0xFF. */ |
|||
|
|||
uint32_t Alpha0; /*!< Configures the default alpha value.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x00 and Max_Data = 0xFF. */ |
|||
|
|||
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
|
|||
This parameter can be one of value of @ref LTDC_BlendingFactor1 */ |
|||
|
|||
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
|
|||
This parameter can be one of value of @ref LTDC_BlendingFactor2 */ |
|||
|
|||
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ |
|||
|
|||
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x0000 and Max_Data = 0x1FFF. */ |
|||
|
|||
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
|
|||
This parameter must be a number between |
|||
Min_Data = 0x000 and Max_Data = 0x7FF. */ |
|||
|
|||
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ |
|||
} LTDC_LayerCfgTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL LTDC State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ |
|||
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ |
|||
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ |
|||
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ |
|||
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ |
|||
} HAL_LTDC_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief LTDC handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) |
|||
typedef struct __LTDC_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ |
|||
{ |
|||
LTDC_TypeDef *Instance; /*!< LTDC Register base address */ |
|||
|
|||
LTDC_InitTypeDef Init; /*!< LTDC parameters */ |
|||
|
|||
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< LTDC Lock */ |
|||
|
|||
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< LTDC Error code */ |
|||
|
|||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) |
|||
void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ |
|||
void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ |
|||
void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ |
|||
|
|||
void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ |
|||
|
|||
|
|||
} LTDC_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL LTDC Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ |
|||
HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ |
|||
|
|||
HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ |
|||
HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ |
|||
HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ |
|||
|
|||
} HAL_LTDC_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL LTDC Callback pointer definition |
|||
*/ |
|||
typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ |
|||
|
|||
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Error_Code LTDC Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ |
|||
#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ |
|||
#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ |
|||
#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ |
|||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) |
|||
#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ |
|||
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Layer LTDC Layer
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ |
|||
#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ |
|||
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ |
|||
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ |
|||
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ |
|||
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_SYNC LTDC SYNC
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ |
|||
#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_COLOR 0x000000FFU /*!< Color mask */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ |
|||
#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ |
|||
#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Pixelformat LTDC Pixel format
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ |
|||
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Alpha LTDC Alpha
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ |
|||
#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ |
|||
|
|||
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ |
|||
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Interrupts LTDC Interrupts
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ |
|||
#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ |
|||
#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ |
|||
#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Flags LTDC Flags
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ |
|||
#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ |
|||
#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ |
|||
#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup LTDC_Reload_Type LTDC Reload Type
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ |
|||
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset LTDC handle state.
|
|||
* @param __HANDLE__ LTDC handle |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) |
|||
#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable the LTDC. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) |
|||
|
|||
/**
|
|||
* @brief Disable the LTDC. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) |
|||
|
|||
/**
|
|||
* @brief Enable the LTDC Layer. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __LAYER__ Specify the layer to be enabled. |
|||
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ |
|||
|= (uint32_t)LTDC_LxCR_LEN) |
|||
|
|||
/**
|
|||
* @brief Disable the LTDC Layer. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __LAYER__ Specify the layer to be disabled. |
|||
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ |
|||
&= ~(uint32_t)LTDC_LxCR_LEN) |
|||
|
|||
/**
|
|||
* @brief Reload immediately all LTDC Layers. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) |
|||
|
|||
/**
|
|||
* @brief Reload during vertical blanking period all LTDC Layers. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) |
|||
|
|||
/* Interrupt & Flag management */ |
|||
/**
|
|||
* @brief Get the LTDC pending flags. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __FLAG__ Get the specified flag. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg LTDC_FLAG_LI: Line Interrupt flag |
|||
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag |
|||
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag |
|||
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag |
|||
* @retval The state of FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clears the LTDC pending flags. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __FLAG__ Specify the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg LTDC_FLAG_LI: Line Interrupt flag |
|||
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag |
|||
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag |
|||
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Enables the specified LTDC interrupts. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg LTDC_IT_LI: Line Interrupt flag |
|||
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag |
|||
* @arg LTDC_IT_TE: Transfer Error interrupt flag |
|||
* @arg LTDC_IT_RR: Register Reload Interrupt Flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disables the specified LTDC interrupts. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg LTDC_IT_LI: Line Interrupt flag |
|||
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag |
|||
* @arg LTDC_IT_TE: Transfer Error interrupt flag |
|||
* @arg LTDC_IT_RR: Register Reload Interrupt Flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified LTDC interrupt has occurred or not. |
|||
* @param __HANDLE__ LTDC handle |
|||
* @param __INTERRUPT__ Specify the LTDC interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg LTDC_IT_LI: Line Interrupt flag |
|||
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag |
|||
* @arg LTDC_IT_TE: Transfer Error interrupt flag |
|||
* @arg LTDC_IT_RR: Register Reload Interrupt Flag |
|||
* @retval The state of INTERRUPT (SET or RESET). |
|||
*/ |
|||
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include LTDC HAL Extension module */ |
|||
#include "stm32f4xx_hal_ltdc_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup LTDC_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
/** @addtogroup LTDC_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions *****************************/ |
|||
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); |
|||
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); |
|||
void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); |
|||
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); |
|||
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); |
|||
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); |
|||
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, |
|||
pLTDC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LTDC_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *****************************************************/ |
|||
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LTDC_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ***********************************************/ |
|||
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); |
|||
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); |
|||
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); |
|||
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); |
|||
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, |
|||
uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, |
|||
uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, |
|||
uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup LTDC_Exported_Functions_Group4
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions *************************************************/ |
|||
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); |
|||
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup LTDC_Private_Macros LTDC Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ |
|||
((uint32_t)((__HANDLE__)->Instance))\ |
|||
+ 0x84U + (0x80U*(__LAYER__))))) |
|||
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) |
|||
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ |
|||
|| ((__HSPOL__) == LTDC_HSPOLARITY_AH)) |
|||
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ |
|||
|| ((__VSPOL__) == LTDC_VSPOLARITY_AH)) |
|||
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ |
|||
|| ((__DEPOL__) == LTDC_DEPOLARITY_AH)) |
|||
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ |
|||
|| ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) |
|||
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) |
|||
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) |
|||
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) |
|||
#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) |
|||
#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) |
|||
#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) |
|||
#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) |
|||
#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) |
|||
#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) |
|||
#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) |
|||
#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) |
|||
#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ |
|||
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) |
|||
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ |
|||
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) |
|||
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ |
|||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) |
|||
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) |
|||
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) |
|||
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) |
|||
#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) |
|||
#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) |
|||
#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) |
|||
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) |
|||
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) |
|||
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) |
|||
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ |
|||
((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup LTDC_Private_Functions LTDC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* LTDC */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_LTDC_H */ |
|||
|
|||
@ -0,0 +1,83 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_ltdc_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of LTDC HAL Extension module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_LTDC_EX_H |
|||
#define STM32F4xx_HAL_LTDC_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
#if defined (LTDC) && defined (DSI) |
|||
|
|||
#include "stm32f4xx_hal_dsi.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup LTDCEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup LTDCEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup LTDCEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); |
|||
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* LTDC && DSI */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_LTDC_EX_H */ |
|||
@ -0,0 +1,747 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_mmc.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of MMC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_MMC_H |
|||
#define STM32F4xx_HAL_MMC_H |
|||
|
|||
#if defined(SDIO) |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_ll_sdmmc.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup MMC
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Exported_Types MMC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */ |
|||
HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */ |
|||
HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */ |
|||
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ |
|||
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ |
|||
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ |
|||
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */ |
|||
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ |
|||
}HAL_MMC_StateTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
|
|||
* @{ |
|||
*/ |
|||
typedef uint32_t HAL_MMC_CardStateTypeDef; |
|||
|
|||
#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ |
|||
#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ |
|||
#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ |
|||
#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ |
|||
#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ |
|||
#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ |
|||
#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ |
|||
#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ |
|||
#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
|
|||
* @{ |
|||
*/ |
|||
#define MMC_InitTypeDef SDIO_InitTypeDef |
|||
#define MMC_TypeDef SDIO_TypeDef |
|||
|
|||
/**
|
|||
* @brief MMC Card Information Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t CardType; /*!< Specifies the card Type */ |
|||
|
|||
uint32_t Class; /*!< Specifies the class of the card class */ |
|||
|
|||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ |
|||
|
|||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ |
|||
|
|||
uint32_t BlockSize; /*!< Specifies one block size in bytes */ |
|||
|
|||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ |
|||
|
|||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ |
|||
|
|||
}HAL_MMC_CardInfoTypeDef; |
|||
|
|||
/**
|
|||
* @brief MMC handle Structure definition |
|||
*/ |
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
typedef struct __MMC_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
|||
{ |
|||
MMC_TypeDef *Instance; /*!< MMC registers base address */ |
|||
|
|||
MMC_InitTypeDef Init; /*!< MMC required parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< MMC locking object */ |
|||
|
|||
uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ |
|||
|
|||
uint32_t TxXferSize; /*!< MMC Tx Transfer size */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ |
|||
|
|||
uint32_t RxXferSize; /*!< MMC Rx Transfer size */ |
|||
|
|||
__IO uint32_t Context; /*!< MMC transfer context */ |
|||
|
|||
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ |
|||
|
|||
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ |
|||
|
|||
uint32_t CSD[4U]; /*!< MMC card specific data table */ |
|||
|
|||
uint32_t CID[4U]; /*!< MMC card identification number table */ |
|||
|
|||
uint32_t Ext_CSD[128]; |
|||
|
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); |
|||
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); |
|||
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); |
|||
void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); |
|||
|
|||
void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); |
|||
void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); |
|||
#endif |
|||
}MMC_HandleTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t CSDStruct; /*!< CSD structure */ |
|||
__IO uint8_t SysSpecVersion; /*!< System specification version */ |
|||
__IO uint8_t Reserved1; /*!< Reserved */ |
|||
__IO uint8_t TAAC; /*!< Data read access time 1 */ |
|||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ |
|||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ |
|||
__IO uint16_t CardComdClasses; /*!< Card command classes */ |
|||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */ |
|||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ |
|||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ |
|||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ |
|||
__IO uint8_t DSRImpl; /*!< DSR implemented */ |
|||
__IO uint8_t Reserved2; /*!< Reserved */ |
|||
__IO uint32_t DeviceSize; /*!< Device Size */ |
|||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ |
|||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ |
|||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ |
|||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ |
|||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ |
|||
__IO uint8_t EraseGrSize; /*!< Erase group size */ |
|||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ |
|||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */ |
|||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ |
|||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ |
|||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */ |
|||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ |
|||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ |
|||
__IO uint8_t Reserved3; /*!< Reserved */ |
|||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */ |
|||
__IO uint8_t FileFormatGroup; /*!< File format group */ |
|||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ |
|||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */ |
|||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */ |
|||
__IO uint8_t FileFormat; /*!< File format */ |
|||
__IO uint8_t ECC; /*!< ECC code */ |
|||
__IO uint8_t CSD_CRC; /*!< CSD CRC */ |
|||
__IO uint8_t Reserved4; /*!< Always 1 */ |
|||
|
|||
}HAL_MMC_CardCSDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */ |
|||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ |
|||
__IO uint32_t ProdName1; /*!< Product Name part1 */ |
|||
__IO uint8_t ProdName2; /*!< Product Name part2 */ |
|||
__IO uint8_t ProdRev; /*!< Product Revision */ |
|||
__IO uint32_t ProdSN; /*!< Product Serial Number */ |
|||
__IO uint8_t Reserved1; /*!< Reserved1 */ |
|||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */ |
|||
__IO uint8_t CID_CRC; /*!< CID CRC */ |
|||
__IO uint8_t Reserved2; /*!< Always 1 */ |
|||
|
|||
}HAL_MMC_CardCIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ |
|||
HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ |
|||
HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ |
|||
HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ |
|||
|
|||
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ |
|||
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ |
|||
}HAL_MMC_CallbackIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
|
|||
* @{ |
|||
*/ |
|||
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup MMC_Exported_Constants Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */ |
|||
|
|||
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
|
|||
* @{ |
|||
*/ |
|||
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ |
|||
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ |
|||
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ |
|||
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ |
|||
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ |
|||
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ |
|||
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ |
|||
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ |
|||
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the |
|||
number of transferred bytes does not match the block length */ |
|||
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ |
|||
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ |
|||
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ |
|||
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock |
|||
command or if there was an attempt to access a locked card */ |
|||
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ |
|||
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ |
|||
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ |
|||
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ |
|||
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ |
|||
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ |
|||
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ |
|||
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ |
|||
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ |
|||
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ |
|||
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out |
|||
of erase sequence command was received */ |
|||
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ |
|||
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ |
|||
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ |
|||
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ |
|||
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ |
|||
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ |
|||
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ |
|||
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ |
|||
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ |
|||
|
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
|
|||
* @{ |
|||
*/ |
|||
#define MMC_CONTEXT_NONE 0x00000000U /*!< None */ |
|||
#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ |
|||
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ |
|||
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ |
|||
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ |
|||
#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ |
|||
#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief |
|||
*/ |
|||
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ |
|||
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ |
|||
#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ |
|||
#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ |
|||
#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ |
|||
#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ |
|||
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
|
|||
* @{ |
|||
*/ |
|||
#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */ |
|||
#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
|||
* @brief macros to handle interrupts and specific clock configurations |
|||
* @{ |
|||
*/ |
|||
/** @brief Reset MMC handle state.
|
|||
* @param __HANDLE__ : MMC handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_MMC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) |
|||
#endif |
|||
|
|||
/**
|
|||
* @brief Enable the MMC device. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Disable the MMC device. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Enable the SDMMC DMA transfer. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Disable the SDMMC DMA transfer. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Enable the MMC device interrupt. |
|||
* @param __HANDLE__: MMC Handle |
|||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the MMC device interrupt. |
|||
* @param __HANDLE__: MMC Handle |
|||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified MMC flag is set or not. |
|||
* @param __HANDLE__: MMC Handle |
|||
* @param __FLAG__: specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress |
|||
* @arg SDIO_FLAG_TXACT: Data transmit in progress |
|||
* @arg SDIO_FLAG_RXACT: Data receive in progress |
|||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
|||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
|||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
|||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
|||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
|||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
|||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
|||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
|||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
|||
* @retval The new state of MMC FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the MMC's pending flags. |
|||
* @param __HANDLE__: MMC Handle |
|||
* @param __FLAG__: specifies the flag to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified MMC interrupt has occurred or not. |
|||
* @param __HANDLE__: MMC Handle |
|||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @retval The new state of MMC IT (SET or RESET). |
|||
*/ |
|||
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Clear the MMC's interrupt pending bits. |
|||
* @param __HANDLE__: MMC Handle |
|||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup MMC_Exported_Functions MMC Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); |
|||
/* Non-Blocking mode: IT */ |
|||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
|
|||
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); |
|||
|
|||
/* Callback in non blocking modes (DMA) */ |
|||
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); |
|||
|
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
/* MMC callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
|||
* @{ |
|||
*/ |
|||
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
|||
* @{ |
|||
*/ |
|||
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); |
|||
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Types MMC Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Defines MMC Private Defines
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Variables MMC Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Constants MMC Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Macros MMC Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Functions MMC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* SDIO */ |
|||
|
|||
#endif /* STM32F4xx_HAL_MMC_H */ |
|||
@ -0,0 +1,388 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_nand.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of NAND HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_NAND_H |
|||
#define STM32F4xx_HAL_NAND_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#if defined(FSMC_Bank2_3) |
|||
#include "stm32f4xx_ll_fsmc.h" |
|||
#else |
|||
#include "stm32f4xx_ll_fmc.h" |
|||
#endif /* FSMC_Bank2_3 */ |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup NAND
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported typedef ----------------------------------------------------------*/ |
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup NAND_Exported_Types NAND Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL NAND State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ |
|||
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ |
|||
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ |
|||
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ |
|||
} HAL_NAND_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief NAND Memory electronic signature Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
/*<! NAND memory electronic signature maker and device IDs */ |
|||
|
|||
uint8_t Maker_Id; |
|||
|
|||
uint8_t Device_Id; |
|||
|
|||
uint8_t Third_Id; |
|||
|
|||
uint8_t Fourth_Id; |
|||
} NAND_IDTypeDef; |
|||
|
|||
/**
|
|||
* @brief NAND Memory address Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint16_t Page; /*!< NAND memory Page address */ |
|||
|
|||
uint16_t Plane; /*!< NAND memory Zone address */ |
|||
|
|||
uint16_t Block; /*!< NAND memory Block address */ |
|||
|
|||
} NAND_AddressTypeDef; |
|||
|
|||
/**
|
|||
* @brief NAND Memory info Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
|||
for 8 bits addressing or words for 16 bits addressing */ |
|||
|
|||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
|||
for 8 bits addressing or words for 16 bits addressing */ |
|||
|
|||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ |
|||
|
|||
uint32_t BlockNbr; /*!< NAND memory number of total blocks */ |
|||
|
|||
uint32_t PlaneNbr; /*!< NAND memory number of planes */ |
|||
|
|||
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ |
|||
|
|||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
|||
parameter is mandatory for some NAND parts after the read |
|||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. |
|||
Example: Toshiba THTH58BYG3S0HBAI6. |
|||
This parameter could be ENABLE or DISABLE |
|||
Please check the Read Mode sequnece in the NAND device datasheet */ |
|||
} NAND_DeviceConfigTypeDef; |
|||
|
|||
/**
|
|||
* @brief NAND handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
|||
typedef struct __NAND_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
|||
{ |
|||
FMC_NAND_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< NAND locking object */ |
|||
|
|||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ |
|||
|
|||
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ |
|||
|
|||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
|||
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ |
|||
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ |
|||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
|||
} NAND_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL NAND Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ |
|||
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ |
|||
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ |
|||
} HAL_NAND_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL NAND Callback pointer definition |
|||
*/ |
|||
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); |
|||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset NAND handle state
|
|||
* @param __HANDLE__ specifies the NAND handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_NAND_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) |
|||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, |
|||
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); |
|||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); |
|||
|
|||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); |
|||
|
|||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); |
|||
|
|||
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); |
|||
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); |
|||
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); |
|||
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* IO operation functions ****************************************************/ |
|||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); |
|||
|
|||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, |
|||
uint32_t NumPageToRead); |
|||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, |
|||
uint32_t NumPageToWrite); |
|||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
|||
uint8_t *pBuffer, uint32_t NumSpareAreaToRead); |
|||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
|||
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); |
|||
|
|||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, |
|||
uint32_t NumPageToRead); |
|||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, |
|||
uint32_t NumPageToWrite); |
|||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
|||
uint16_t *pBuffer, uint32_t NumSpareAreaToRead); |
|||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, |
|||
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); |
|||
|
|||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
|||
|
|||
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
|||
|
|||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) |
|||
/* NAND callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, |
|||
pNAND_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); |
|||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* NAND Control functions ****************************************************/ |
|||
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); |
|||
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); |
|||
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
|
|||
* @{ |
|||
*/ |
|||
/* NAND State functions *******************************************************/ |
|||
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); |
|||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup NAND_Private_Constants NAND Private Constants
|
|||
* @{ |
|||
*/ |
|||
#if defined(FMC_Bank2_3) |
|||
#define NAND_DEVICE1 0x70000000UL |
|||
#define NAND_DEVICE2 0x80000000UL |
|||
#else |
|||
#define NAND_DEVICE 0x80000000UL |
|||
#endif |
|||
#define NAND_WRITE_TIMEOUT 0x01000000UL |
|||
|
|||
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ |
|||
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ |
|||
|
|||
#define NAND_CMD_AREA_A ((uint8_t)0x00) |
|||
#define NAND_CMD_AREA_B ((uint8_t)0x01) |
|||
#define NAND_CMD_AREA_C ((uint8_t)0x50) |
|||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) |
|||
|
|||
#define NAND_CMD_WRITE0 ((uint8_t)0x80) |
|||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) |
|||
#define NAND_CMD_ERASE0 ((uint8_t)0x60) |
|||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0) |
|||
#define NAND_CMD_READID ((uint8_t)0x90) |
|||
#define NAND_CMD_STATUS ((uint8_t)0x70) |
|||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) |
|||
#define NAND_CMD_RESET ((uint8_t)0xFF) |
|||
|
|||
/* NAND memory status */ |
|||
#define NAND_VALID_ADDRESS 0x00000100UL |
|||
#define NAND_INVALID_ADDRESS 0x00000200UL |
|||
#define NAND_TIMEOUT_ERROR 0x00000400UL |
|||
#define NAND_BUSY 0x00000000UL |
|||
#define NAND_ERROR 0x00000001UL |
|||
#define NAND_READY 0x00000040UL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup NAND_Private_Macros NAND Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief NAND memory address computation. |
|||
* @param __ADDRESS__ NAND memory address. |
|||
* @param __HANDLE__ NAND handle. |
|||
* @retval NAND Raw address value |
|||
*/ |
|||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ |
|||
(((__ADDRESS__)->Block + \ |
|||
(((__ADDRESS__)->Plane) * \ |
|||
((__HANDLE__)->Config.PlaneSize))) * \ |
|||
((__HANDLE__)->Config.BlockSize))) |
|||
|
|||
/**
|
|||
* @brief NAND memory Column address computation. |
|||
* @param __HANDLE__ NAND handle. |
|||
* @retval NAND Raw address value |
|||
*/ |
|||
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) |
|||
|
|||
/**
|
|||
* @brief NAND memory address cycling. |
|||
* @param __ADDRESS__ NAND memory address. |
|||
* @retval NAND address cycling value. |
|||
*/ |
|||
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ |
|||
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ |
|||
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ |
|||
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ |
|||
|
|||
/**
|
|||
* @brief NAND memory Columns cycling. |
|||
* @param __ADDRESS__ NAND memory address. |
|||
* @retval NAND Column address cycling value. |
|||
*/ |
|||
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ |
|||
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_NAND_H */ |
|||
@ -0,0 +1,330 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_nor.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of NOR HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_NOR_H |
|||
#define STM32F4xx_HAL_NOR_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMC_Bank1) || defined(FSMC_Bank1) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#if defined(FSMC_Bank1) |
|||
#include "stm32f4xx_ll_fsmc.h" |
|||
#else |
|||
#include "stm32f4xx_ll_fmc.h" |
|||
#endif /* FMC_Bank1 */ |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup NOR
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported typedef ----------------------------------------------------------*/ |
|||
/** @defgroup NOR_Exported_Types NOR Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL SRAM State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ |
|||
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ |
|||
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ |
|||
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ |
|||
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ |
|||
} HAL_NOR_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief FMC NOR Status typedef |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_NOR_STATUS_SUCCESS = 0U, |
|||
HAL_NOR_STATUS_ONGOING, |
|||
HAL_NOR_STATUS_ERROR, |
|||
HAL_NOR_STATUS_TIMEOUT |
|||
} HAL_NOR_StatusTypeDef; |
|||
|
|||
/**
|
|||
* @brief FMC NOR ID typedef |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ |
|||
|
|||
uint16_t Device_Code1; |
|||
|
|||
uint16_t Device_Code2; |
|||
|
|||
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
|
|||
These codes can be accessed by performing read operations with specific |
|||
control signals and addresses set.They can also be accessed by issuing |
|||
an Auto Select command */ |
|||
} NOR_IDTypeDef; |
|||
|
|||
/**
|
|||
* @brief FMC NOR CFI typedef |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
/*!< Defines the information stored in the memory's Common flash interface
|
|||
which contains a description of various electrical and timing parameters, |
|||
density information and functions supported by the memory */ |
|||
|
|||
uint16_t CFI_1; |
|||
|
|||
uint16_t CFI_2; |
|||
|
|||
uint16_t CFI_3; |
|||
|
|||
uint16_t CFI_4; |
|||
} NOR_CFITypeDef; |
|||
|
|||
/**
|
|||
* @brief NOR handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
|||
typedef struct __NOR_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
|||
|
|||
{ |
|||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
|||
|
|||
FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< NOR locking object */ |
|||
|
|||
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ |
|||
|
|||
uint32_t CommandSet; /*!< NOR algorithm command set and control */ |
|||
|
|||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
|||
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ |
|||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
|||
} NOR_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL NOR Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ |
|||
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ |
|||
} HAL_NOR_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL NOR Callback pointer definition |
|||
*/ |
|||
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); |
|||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup NOR_Exported_Macros NOR Exported Macros
|
|||
* @{ |
|||
*/ |
|||
/** @brief Reset NOR handle state
|
|||
* @param __HANDLE__ specifies the NOR handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_NOR_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) |
|||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, |
|||
FMC_NORSRAM_TimingTypeDef *ExtTiming); |
|||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); |
|||
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); |
|||
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); |
|||
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* I/O operation functions ***************************************************/ |
|||
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); |
|||
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); |
|||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
|||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
|||
|
|||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, |
|||
uint32_t uwBufferSize); |
|||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, |
|||
uint32_t uwBufferSize); |
|||
|
|||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); |
|||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); |
|||
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); |
|||
|
|||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) |
|||
/* NOR callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, |
|||
pNOR_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); |
|||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* NOR Control functions *****************************************************/ |
|||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); |
|||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* NOR State functions ********************************************************/ |
|||
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); |
|||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup NOR_Private_Constants NOR Private Constants
|
|||
* @{ |
|||
*/ |
|||
/* NOR device IDs addresses */ |
|||
#define MC_ADDRESS ((uint16_t)0x0000) |
|||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) |
|||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) |
|||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) |
|||
|
|||
/* NOR CFI IDs addresses */ |
|||
#define CFI1_ADDRESS ((uint16_t)0x0061) |
|||
#define CFI2_ADDRESS ((uint16_t)0x0062) |
|||
#define CFI3_ADDRESS ((uint16_t)0x0063) |
|||
#define CFI4_ADDRESS ((uint16_t)0x0064) |
|||
|
|||
/* NOR operation wait timeout */ |
|||
#define NOR_TMEOUT ((uint16_t)0xFFFF) |
|||
|
|||
/* NOR memory data width */ |
|||
#define NOR_MEMORY_8B ((uint8_t)0x00) |
|||
#define NOR_MEMORY_16B ((uint8_t)0x01) |
|||
|
|||
/* NOR memory device read/write start address */ |
|||
#define NOR_MEMORY_ADRESS1 (0x60000000U) |
|||
#define NOR_MEMORY_ADRESS2 (0x64000000U) |
|||
#define NOR_MEMORY_ADRESS3 (0x68000000U) |
|||
#define NOR_MEMORY_ADRESS4 (0x6C000000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup NOR_Private_Macros NOR Private Macros
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief NOR memory address shifting. |
|||
* @param __NOR_ADDRESS NOR base address |
|||
* @param __NOR_MEMORY_WIDTH_ NOR memory width |
|||
* @param __ADDRESS__ NOR memory address |
|||
* @retval NOR shifted address value |
|||
*/ |
|||
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ |
|||
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ |
|||
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ |
|||
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) |
|||
|
|||
/**
|
|||
* @brief NOR memory write data to specified address. |
|||
* @param __ADDRESS__ NOR memory address |
|||
* @param __DATA__ Data to write |
|||
* @retval None |
|||
*/ |
|||
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ |
|||
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ |
|||
__DSB(); \ |
|||
} while(0) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMC_Bank1 || FSMC_Bank1 */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_NOR_H */ |
|||
@ -0,0 +1,285 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_pccard.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of PCCARD HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_PCCARD_H |
|||
#define STM32F4xx_HAL_PCCARD_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMC_Bank4) || defined(FSMC_Bank4) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#if defined(FSMC_Bank4) |
|||
#include "stm32f4xx_ll_fsmc.h" |
|||
#else |
|||
#include "stm32f4xx_ll_fmc.h" |
|||
#endif /* FSMC_Bank4 */ |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup PCCARD
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported typedef ----------------------------------------------------------*/ |
|||
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL PCCARD State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */ |
|||
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */ |
|||
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */ |
|||
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */ |
|||
} HAL_PCCARD_StateTypeDef; |
|||
|
|||
typedef enum |
|||
{ |
|||
HAL_PCCARD_STATUS_SUCCESS = 0U, |
|||
HAL_PCCARD_STATUS_ONGOING, |
|||
HAL_PCCARD_STATUS_ERROR, |
|||
HAL_PCCARD_STATUS_TIMEOUT |
|||
} HAL_PCCARD_StatusTypeDef; |
|||
|
|||
/**
|
|||
* @brief FMC_PCCARD handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) |
|||
typedef struct __PCCARD_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ |
|||
{ |
|||
FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */ |
|||
|
|||
FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */ |
|||
|
|||
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< PCCARD Lock */ |
|||
|
|||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) |
|||
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ |
|||
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ |
|||
#endif |
|||
} PCCARD_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL PCCARD Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */ |
|||
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */ |
|||
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */ |
|||
} HAL_PCCARD_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL PCCARD Callback pointer definition |
|||
*/ |
|||
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
|
|||
* @{ |
|||
*/ |
|||
/** @brief Reset PCCARD handle state
|
|||
* @param __HANDLE__ specifies the PCCARD handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET) |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup PCCARD_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup PCCARD_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, |
|||
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); |
|||
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); |
|||
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); |
|||
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup PCCARD_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *****************************************************/ |
|||
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus); |
|||
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, |
|||
uint8_t *pStatus); |
|||
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, |
|||
uint8_t *pStatus); |
|||
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus); |
|||
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard); |
|||
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard); |
|||
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard); |
|||
|
|||
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) |
|||
/* PCCARD callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, |
|||
pPCCARD_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, |
|||
HAL_PCCARD_CallbackIDTypeDef CallbackId); |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup PCCARD_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* PCCARD State functions *******************************************************/ |
|||
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard); |
|||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard); |
|||
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define PCCARD_DEVICE_ADDRESS 0x90000000U |
|||
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS 0x98000000U /* Attribute space size to @0x9BFF FFFF */ |
|||
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */ |
|||
#define PCCARD_IO_SPACE_ADDRESS 0x9C000000U /* IO space size to @0x9FFF FFFF */ |
|||
#define PCCARD_IO_SPACE_PRIMARY_ADDR 0x9C0001F0U /* IO space size to @0x9FFF FFFF */ |
|||
|
|||
/* Flash-ATA registers description */ |
|||
#define ATA_DATA ((uint8_t)0x00) /* Data register */ |
|||
#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */ |
|||
#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */ |
|||
#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */ |
|||
#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */ |
|||
#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */ |
|||
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */ |
|||
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */ |
|||
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */ |
|||
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */ |
|||
|
|||
/* Flash-ATA commands */ |
|||
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20) |
|||
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30) |
|||
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0) |
|||
#define ATA_IDENTIFY_CMD ((uint8_t)0xEC) |
|||
|
|||
/* PC Card/Compact Flash status */ |
|||
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60) |
|||
#define PCCARD_BUSY ((uint8_t)0x80) |
|||
#define PCCARD_PROGR ((uint8_t)0x01) |
|||
#define PCCARD_READY ((uint8_t)0x40) |
|||
|
|||
#define PCCARD_SECTOR_SIZE 255U /* In half words */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Compact Flash redefinition */ |
|||
#define HAL_CF_Init HAL_PCCARD_Init |
|||
#define HAL_CF_DeInit HAL_PCCARD_DeInit |
|||
#define HAL_CF_MspInit HAL_PCCARD_MspInit |
|||
#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit |
|||
|
|||
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID |
|||
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector |
|||
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector |
|||
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector |
|||
#define HAL_CF_Reset HAL_PCCARD_Reset |
|||
#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler |
|||
#define HAL_CF_ITCallback HAL_PCCARD_ITCallback |
|||
|
|||
#define HAL_CF_GetState HAL_PCCARD_GetState |
|||
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus |
|||
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus |
|||
|
|||
#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS |
|||
#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING |
|||
#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR |
|||
#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT |
|||
#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef |
|||
|
|||
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS |
|||
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS |
|||
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS |
|||
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS |
|||
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR |
|||
|
|||
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR |
|||
#define CF_BUSY PCCARD_BUSY |
|||
#define CF_PROGR PCCARD_PROGR |
|||
#define CF_READY PCCARD_READY |
|||
|
|||
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMC_Bank4 || FSMC_Bank4 */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_PCCARD_H */ |
|||
@ -0,0 +1,750 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_qspi.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of QSPI HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_QSPI_H |
|||
#define STM32F4xx_HAL_QSPI_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
#if defined(QUADSPI) |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup QSPI
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup QSPI_Exported_Types QSPI Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief QSPI Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
|
|||
This parameter can be a number between 0 and 255 */ |
|||
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
|
|||
This parameter can be a value between 1 and 32 */ |
|||
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
|
|||
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) |
|||
This parameter can be a value of @ref QSPI_SampleShifting */ |
|||
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
|
|||
required to address the flash memory. The flash capacity can be up to 4GB |
|||
(addressed using 32 bits) in indirect mode, but the addressable space in |
|||
memory-mapped mode is limited to 256MB |
|||
This parameter can be a number between 0 and 31 */ |
|||
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
|
|||
of clock cycles which the chip select must remain high between commands. |
|||
This parameter can be a value of @ref QSPI_ChipSelectHighTime */ |
|||
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
|
|||
This parameter can be a value of @ref QSPI_ClockMode */ |
|||
uint32_t FlashID; /* Specifies the Flash which will be used,
|
|||
This parameter can be a value of @ref QSPI_Flash_Select */ |
|||
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
|
|||
This parameter can be a value of @ref QSPI_DualFlash_Mode */ |
|||
}QSPI_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL QSPI State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ |
|||
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ |
|||
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ |
|||
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ |
|||
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ |
|||
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ |
|||
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ |
|||
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ |
|||
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ |
|||
}HAL_QSPI_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief QSPI Handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) |
|||
typedef struct __QSPI_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif |
|||
{ |
|||
QUADSPI_TypeDef *Instance; /* QSPI registers base address */ |
|||
QSPI_InitTypeDef Init; /* QSPI communication parameters */ |
|||
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ |
|||
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ |
|||
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ |
|||
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ |
|||
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ |
|||
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ |
|||
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ |
|||
__IO HAL_LockTypeDef Lock; /* Locking object */ |
|||
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ |
|||
__IO uint32_t ErrorCode; /* QSPI Error code */ |
|||
uint32_t Timeout; /* Timeout for the QSPI memory access */ |
|||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) |
|||
void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
|
|||
void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); |
|||
#endif |
|||
}QSPI_HandleTypeDef; |
|||
|
|||
/**
|
|||
* @brief QSPI Command structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Instruction; /* Specifies the Instruction to be sent
|
|||
This parameter can be a value (8-bit) between 0x00 and 0xFF */ |
|||
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
|
|||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
|||
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
|
|||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
|||
uint32_t AddressSize; /* Specifies the Address Size
|
|||
This parameter can be a value of @ref QSPI_AddressSize */ |
|||
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
|
|||
This parameter can be a value of @ref QSPI_AlternateBytesSize */ |
|||
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
|
|||
This parameter can be a number between 0 and 31 */ |
|||
uint32_t InstructionMode; /* Specifies the Instruction Mode
|
|||
This parameter can be a value of @ref QSPI_InstructionMode */ |
|||
uint32_t AddressMode; /* Specifies the Address Mode
|
|||
This parameter can be a value of @ref QSPI_AddressMode */ |
|||
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
|
|||
This parameter can be a value of @ref QSPI_AlternateBytesMode */ |
|||
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
|
|||
This parameter can be a value of @ref QSPI_DataMode */ |
|||
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
|
|||
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length |
|||
until end of memory)*/ |
|||
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
|
|||
This parameter can be a value of @ref QSPI_DdrMode */ |
|||
uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
|
|||
output by one half of system clock in DDR mode. |
|||
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ |
|||
uint32_t SIOOMode; /* Specifies the send instruction only once mode
|
|||
This parameter can be a value of @ref QSPI_SIOOMode */ |
|||
}QSPI_CommandTypeDef; |
|||
|
|||
/**
|
|||
* @brief QSPI Auto Polling mode configuration structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
|
|||
This parameter can be any value between 0 and 0xFFFFFFFF */ |
|||
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
|
|||
This parameter can be any value between 0 and 0xFFFFFFFF */ |
|||
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
|
|||
This parameter can be any value between 0 and 0xFFFF */ |
|||
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
|
|||
This parameter can be any value between 1 and 4 */ |
|||
uint32_t MatchMode; /* Specifies the method used for determining a match.
|
|||
This parameter can be a value of @ref QSPI_MatchMode */ |
|||
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
|
|||
This parameter can be a value of @ref QSPI_AutomaticStop */ |
|||
}QSPI_AutoPollingTypeDef; |
|||
|
|||
/**
|
|||
* @brief QSPI Memory Mapped mode configuration structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
|
|||
This parameter can be any value between 0 and 0xFFFF */ |
|||
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
|
|||
This parameter can be a value of @ref QSPI_TimeOutActivation */ |
|||
}QSPI_MemoryMappedTypeDef; |
|||
|
|||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL QSPI Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ |
|||
HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ |
|||
HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ |
|||
HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ |
|||
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ |
|||
HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ |
|||
HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ |
|||
HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ |
|||
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ |
|||
HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ |
|||
|
|||
HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ |
|||
HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ |
|||
}HAL_QSPI_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL QSPI Callback pointer definition |
|||
*/ |
|||
typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_ErrorCode QSPI Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ |
|||
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ |
|||
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ |
|||
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ |
|||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) |
|||
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ |
|||
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ |
|||
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_ClockMode QSPI Clock Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ |
|||
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_Flash_Select QSPI Flash Select
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ |
|||
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ |
|||
#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_AddressSize QSPI Address Size
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ |
|||
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ |
|||
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ |
|||
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ |
|||
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ |
|||
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ |
|||
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ |
|||
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ |
|||
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ |
|||
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_AddressMode QSPI Address Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ |
|||
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ |
|||
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ |
|||
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ |
|||
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ |
|||
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ |
|||
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_DataMode QSPI Data Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/ |
|||
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ |
|||
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ |
|||
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_DdrMode QSPI DDR Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ |
|||
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ |
|||
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ |
|||
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_MatchMode QSPI Match Mode
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ |
|||
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ |
|||
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ |
|||
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_Flags QSPI Flags
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ |
|||
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ |
|||
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ |
|||
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ |
|||
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ |
|||
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_Interrupts QSPI Interrupts
|
|||
* @{ |
|||
*/ |
|||
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ |
|||
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ |
|||
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ |
|||
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ |
|||
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
|
|||
* @brief QSPI Timeout definition |
|||
* @{ |
|||
*/ |
|||
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
|
|||
* @{ |
|||
*/ |
|||
/** @brief Reset QSPI handle state.
|
|||
* @param __HANDLE__ QSPI handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) |
|||
#endif |
|||
|
|||
/** @brief Enable the QSPI peripheral.
|
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
|||
|
|||
/** @brief Disable the QSPI peripheral.
|
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
|||
|
|||
/** @brief Enable the specified QSPI interrupt.
|
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @param __INTERRUPT__ specifies the QSPI interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg QSPI_IT_TO: QSPI Timeout interrupt |
|||
* @arg QSPI_IT_SM: QSPI Status match interrupt |
|||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
|||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
|||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
|||
|
|||
|
|||
/** @brief Disable the specified QSPI interrupt.
|
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @param __INTERRUPT__ specifies the QSPI interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg QSPI_IT_TO: QSPI Timeout interrupt |
|||
* @arg QSPI_IT_SM: QSPI Status match interrupt |
|||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
|||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
|||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
|||
|
|||
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
|
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @param __INTERRUPT__ specifies the QSPI interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg QSPI_IT_TO: QSPI Timeout interrupt |
|||
* @arg QSPI_IT_SM: QSPI Status match interrupt |
|||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
|||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
|||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt |
|||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the selected QSPI flag is set or not. |
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @param __FLAG__ specifies the QSPI flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg QSPI_FLAG_BUSY: QSPI Busy flag |
|||
* @arg QSPI_FLAG_TO: QSPI Timeout flag |
|||
* @arg QSPI_FLAG_SM: QSPI Status match flag |
|||
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag |
|||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
|||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) |
|||
|
|||
/** @brief Clears the specified QSPI's flag status.
|
|||
* @param __HANDLE__ specifies the QSPI Handle. |
|||
* @param __FLAG__ specifies the QSPI clear register flag that needs to be set |
|||
* This parameter can be one of the following values: |
|||
* @arg QSPI_FLAG_TO: QSPI Timeout flag |
|||
* @arg QSPI_FLAG_SM: QSPI Status match flag |
|||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
|||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup QSPI_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup QSPI_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); |
|||
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup QSPI_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *****************************************************/ |
|||
/* QSPI IRQ handler method */ |
|||
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); |
|||
|
|||
/* QSPI indirect mode */ |
|||
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); |
|||
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
|||
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
|||
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
|||
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
|||
|
|||
/* QSPI status flag polling mode */ |
|||
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); |
|||
|
|||
/* QSPI memory-mapped mode */ |
|||
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); |
|||
|
|||
/* Callback functions in non-blocking modes ***********************************/ |
|||
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); |
|||
|
|||
/* QSPI indirect mode */ |
|||
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
|||
|
|||
/* QSPI status flag polling mode */ |
|||
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); |
|||
|
|||
/* QSPI memory-mapped mode */ |
|||
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); |
|||
|
|||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) |
|||
/* QSPI callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup QSPI_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control and State functions ************************************/ |
|||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); |
|||
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); |
|||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); |
|||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); |
|||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); |
|||
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); |
|||
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* End of exported functions -------------------------------------------------*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup QSPI_Private_Macros QSPI Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) |
|||
|
|||
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) |
|||
|
|||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ |
|||
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) |
|||
|
|||
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) |
|||
|
|||
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ |
|||
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) |
|||
|
|||
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ |
|||
((CLKMODE) == QSPI_CLOCK_MODE_3)) |
|||
|
|||
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ |
|||
((FLASH_ID) == QSPI_FLASH_ID_2)) |
|||
|
|||
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ |
|||
((MODE) == QSPI_DUALFLASH_DISABLE)) |
|||
|
|||
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) |
|||
|
|||
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ |
|||
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ |
|||
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ |
|||
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) |
|||
|
|||
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ |
|||
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ |
|||
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ |
|||
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) |
|||
|
|||
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) |
|||
|
|||
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ |
|||
((MODE) == QSPI_INSTRUCTION_1_LINE) || \ |
|||
((MODE) == QSPI_INSTRUCTION_2_LINES) || \ |
|||
((MODE) == QSPI_INSTRUCTION_4_LINES)) |
|||
|
|||
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ |
|||
((MODE) == QSPI_ADDRESS_1_LINE) || \ |
|||
((MODE) == QSPI_ADDRESS_2_LINES) || \ |
|||
((MODE) == QSPI_ADDRESS_4_LINES)) |
|||
|
|||
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ |
|||
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ |
|||
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ |
|||
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) |
|||
|
|||
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ |
|||
((MODE) == QSPI_DATA_1_LINE) || \ |
|||
((MODE) == QSPI_DATA_2_LINES) || \ |
|||
((MODE) == QSPI_DATA_4_LINES)) |
|||
|
|||
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ |
|||
((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) |
|||
|
|||
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ |
|||
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) |
|||
|
|||
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ |
|||
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) |
|||
|
|||
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) |
|||
|
|||
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) |
|||
|
|||
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ |
|||
((MODE) == QSPI_MATCH_MODE_OR)) |
|||
|
|||
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ |
|||
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) |
|||
|
|||
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ |
|||
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) |
|||
|
|||
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* End of private macros -----------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* defined(QUADSPI) */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_QSPI_H */ |
|||
@ -0,0 +1,922 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_rtc.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of RTC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_RTC_H |
|||
#define STM32F4xx_HAL_RTC_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
|
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup RTC
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ |
|||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ |
|||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ |
|||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ |
|||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ |
|||
} HAL_RTCStateTypeDef; |
|||
|
|||
/**
|
|||
* @brief RTC Configuration Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
|||
This parameter can be a value of @ref RTC_Hour_Formats */ |
|||
|
|||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
|||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ |
|||
|
|||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
|||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */ |
|||
|
|||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
|||
This parameter can be a value of @ref RTC_Output_selection_Definitions */ |
|||
|
|||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
|||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ |
|||
|
|||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
|||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ |
|||
} RTC_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief RTC Time structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected |
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ |
|||
|
|||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ |
|||
|
|||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ |
|||
|
|||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
|||
This parameter can be a value of @ref RTC_AM_PM_Definitions */ |
|||
|
|||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
|||
This parameter corresponds to a time unit range between [0-1] Second |
|||
with [1 Sec / SecondFraction +1] granularity */ |
|||
|
|||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
|||
corresponding to Synchronous prescaler factor value (PREDIV_S) |
|||
This parameter corresponds to a time unit range between [0-1] Second |
|||
with [1 Sec / SecondFraction +1] granularity. |
|||
This field will be used only by HAL_RTC_GetTime function */ |
|||
|
|||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight
|
|||
Saving Time, please use HAL_RTC_DST_xxx functions */ |
|||
|
|||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight
|
|||
Saving Time, please use HAL_RTC_DST_xxx functions */ |
|||
} RTC_TimeTypeDef; |
|||
|
|||
/**
|
|||
* @brief RTC Date structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
|||
This parameter can be a value of @ref RTC_WeekDay_Definitions */ |
|||
|
|||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
|||
This parameter can be a value of @ref RTC_Month_Date_Definitions */ |
|||
|
|||
uint8_t Date; /*!< Specifies the RTC Date.
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ |
|||
|
|||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ |
|||
|
|||
} RTC_DateTypeDef; |
|||
|
|||
/**
|
|||
* @brief RTC Alarm structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ |
|||
|
|||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
|||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */ |
|||
|
|||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
|||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ |
|||
|
|||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
|||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ |
|||
|
|||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
|||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. |
|||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ |
|||
|
|||
uint32_t Alarm; /*!< Specifies the alarm .
|
|||
This parameter can be a value of @ref RTC_Alarms_Definitions */ |
|||
} RTC_AlarmTypeDef; |
|||
|
|||
/**
|
|||
* @brief RTC Handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) |
|||
typedef struct __RTC_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ |
|||
{ |
|||
RTC_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
RTC_InitTypeDef Init; /*!< RTC required parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< RTC locking object */ |
|||
|
|||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */ |
|||
|
|||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) |
|||
void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ |
|||
|
|||
void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ |
|||
|
|||
void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */ |
|||
|
|||
void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ |
|||
|
|||
void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ |
|||
|
|||
#if defined(RTC_TAMPER2_SUPPORT) |
|||
void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ |
|||
#endif /* RTC_TAMPER2_SUPPORT */ |
|||
|
|||
void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ |
|||
|
|||
void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ |
|||
|
|||
} RTC_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL RTC Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ |
|||
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ |
|||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */ |
|||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */ |
|||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ |
|||
#if defined(RTC_TAMPER2_SUPPORT) |
|||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ |
|||
#endif /* RTC_TAMPER2_SUPPORT */ |
|||
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ |
|||
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ |
|||
} HAL_RTC_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL RTC Callback pointer definition |
|||
*/ |
|||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ |
|||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
|||
* @{ |
|||
*/ |
|||
#define RTC_HOURFORMAT_24 0x00000000U |
|||
#define RTC_HOURFORMAT_12 RTC_CR_FMT |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_OUTPUT_DISABLE 0x00000000U |
|||
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 |
|||
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 |
|||
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U |
|||
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
|||
* @{ |
|||
*/ |
|||
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U |
|||
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) |
|||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x01) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H |
|||
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H |
|||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_STOREOPERATION_RESET 0x00000000U |
|||
#define RTC_STOREOPERATION_SET RTC_CR_BKP |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_FORMAT_BIN 0x00000000U |
|||
#define RTC_FORMAT_BCD 0x00000001U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
|
|||
* @{ |
|||
*/ |
|||
#define RTC_MONTH_JANUARY ((uint8_t)0x01) |
|||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) |
|||
#define RTC_MONTH_MARCH ((uint8_t)0x03) |
|||
#define RTC_MONTH_APRIL ((uint8_t)0x04) |
|||
#define RTC_MONTH_MAY ((uint8_t)0x05) |
|||
#define RTC_MONTH_JUNE ((uint8_t)0x06) |
|||
#define RTC_MONTH_JULY ((uint8_t)0x07) |
|||
#define RTC_MONTH_AUGUST ((uint8_t)0x08) |
|||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) |
|||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10) |
|||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) |
|||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) |
|||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) |
|||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) |
|||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) |
|||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) |
|||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) |
|||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U |
|||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_ALARMMASK_NONE 0x00000000U |
|||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 |
|||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 |
|||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 |
|||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 |
|||
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \ |
|||
RTC_ALARMMASK_HOURS | \ |
|||
RTC_ALARMMASK_MINUTES | \ |
|||
RTC_ALARMMASK_SECONDS) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_ALARM_A RTC_CR_ALRAE |
|||
#define RTC_ALARM_B RTC_CR_ALRBE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
|||
* @{ |
|||
*/ |
|||
/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ |
|||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U |
|||
/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 |
|||
/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 |
|||
/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) |
|||
/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 |
|||
/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) |
|||
/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) |
|||
/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) |
|||
/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 |
|||
/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) |
|||
/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) |
|||
/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) |
|||
/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) |
|||
/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) |
|||
/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */ |
|||
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) |
|||
/*!< SS[14:0] are compared and must match to activate alarm. */ |
|||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ |
|||
#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ |
|||
#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ |
|||
#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
|||
* @{ |
|||
*/ |
|||
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */ |
|||
#if defined(RTC_TAMPER2_SUPPORT) |
|||
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */ |
|||
#endif /* RTC_TAMPER2_SUPPORT */ |
|||
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */ |
|||
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */ |
|||
#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */ |
|||
#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */ |
|||
#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */ |
|||
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */ |
|||
#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */ |
|||
#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */ |
|||
#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */ |
|||
#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */ |
|||
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */ |
|||
#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */ |
|||
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
|
|||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset RTC handle state
|
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_RTC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0U) |
|||
#else |
|||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) |
|||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Disable the write protection for RTC registers. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \ |
|||
(__HANDLE__)->Instance->WPR = 0xCAU; \ |
|||
(__HANDLE__)->Instance->WPR = 0x53U; \ |
|||
} while(0U) |
|||
|
|||
/**
|
|||
* @brief Enable the write protection for RTC registers. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \ |
|||
(__HANDLE__)->Instance->WPR = 0xFFU; \ |
|||
} while(0U) |
|||
|
|||
|
|||
/**
|
|||
* @brief Check whether the RTC Calendar is initialized. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) |
|||
|
|||
/**
|
|||
* @brief Enable the RTC ALARMA peripheral. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) |
|||
|
|||
/**
|
|||
* @brief Disable the RTC ALARMA peripheral. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) |
|||
|
|||
/**
|
|||
* @brief Enable the RTC ALARMB peripheral. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) |
|||
|
|||
/**
|
|||
* @brief Disable the RTC ALARMB peripheral. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) |
|||
|
|||
/**
|
|||
* @brief Enable the RTC Alarm interrupt. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg RTC_IT_ALRA: Alarm A interrupt |
|||
* @arg RTC_IT_ALRB: Alarm B interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the RTC Alarm interrupt. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg RTC_IT_ALRA: Alarm A interrupt |
|||
* @arg RTC_IT_ALRB: Alarm B interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. |
|||
* This parameter can be: |
|||
* @arg RTC_IT_ALRA: Alarm A interrupt |
|||
* @arg RTC_IT_ALRB: Alarm B interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) |
|||
|
|||
/**
|
|||
* @brief Get the selected RTC Alarm's flag status. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @param __FLAG__ specifies the RTC Alarm Flag to check. |
|||
* This parameter can be: |
|||
* @arg RTC_FLAG_ALRAF: Alarm A interrupt flag |
|||
* @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag |
|||
* @arg RTC_FLAG_ALRBF: Alarm B interrupt flag |
|||
* @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) |
|||
|
|||
/**
|
|||
* @brief Clear the RTC Alarm's pending flags. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @param __FLAG__ specifies the RTC Alarm flag to be cleared. |
|||
* This parameter can be: |
|||
* @arg RTC_FLAG_ALRAF |
|||
* @arg RTC_FLAG_ALRBF |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not. |
|||
* @param __HANDLE__ specifies the RTC handle. |
|||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. |
|||
* This parameter can be: |
|||
* @arg RTC_IT_ALRA: Alarm A interrupt |
|||
* @arg RTC_IT_ALRB: Alarm B interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) |
|||
|
|||
/**
|
|||
* @brief Enable interrupt on the RTC Alarm associated EXTI line. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable interrupt on the RTC Alarm associated EXTI line. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Enable event on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable event on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Enable falling edge trigger on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable falling edge trigger on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Enable rising edge trigger on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Disable rising edge trigger on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ |
|||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ |
|||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ |
|||
} while(0U) |
|||
|
|||
/**
|
|||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ |
|||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ |
|||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ |
|||
} while(0U) |
|||
|
|||
/**
|
|||
* @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not. |
|||
* @retval Line Status. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Clear the RTC Alarm associated EXTI line flag. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) |
|||
|
|||
/**
|
|||
* @brief Generate a Software interrupt on RTC Alarm associated EXTI line. |
|||
* @retval None. |
|||
*/ |
|||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include RTC HAL Extended module */ |
|||
#include "stm32f4xx_hal_rtc_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup RTC_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup RTC_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions ****************************/ |
|||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); |
|||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); |
|||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); |
|||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup RTC_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* RTC Time and Date functions ************************************************/ |
|||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); |
|||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); |
|||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); |
|||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup RTC_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* RTC Alarm functions ********************************************************/ |
|||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); |
|||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); |
|||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); |
|||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); |
|||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); |
|||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); |
|||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup RTC_Exported_Functions_Group4
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ***********************************************/ |
|||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); |
|||
|
|||
/* RTC Daylight Saving Time functions *****************************************/ |
|||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); |
|||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); |
|||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); |
|||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); |
|||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup RTC_Exported_Functions_Group5
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions *************************************************/ |
|||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
|
|||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
|||
* @{ |
|||
*/ |
|||
/* Masks Definition */ |
|||
#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \ |
|||
RTC_TR_MNT | RTC_TR_MNU | \ |
|||
RTC_TR_ST | RTC_TR_SU | \ |
|||
RTC_TR_PM)) |
|||
#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \ |
|||
RTC_DR_MT | RTC_DR_MU | \ |
|||
RTC_DR_DT | RTC_DR_DU | \ |
|||
RTC_DR_WDU)) |
|||
#define RTC_INIT_MASK 0xFFFFFFFFU |
|||
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) |
|||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \ |
|||
RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \ |
|||
RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \ |
|||
RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \ |
|||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \ |
|||
RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ |
|||
RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK)) |
|||
|
|||
#define RTC_TIMEOUT_VALUE 1000U |
|||
|
|||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
|||
* @{ |
|||
*/ |
|||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ |
|||
((FORMAT) == RTC_HOURFORMAT_24)) |
|||
|
|||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ |
|||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \ |
|||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \ |
|||
((OUTPUT) == RTC_OUTPUT_WAKEUP)) |
|||
|
|||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ |
|||
((POL) == RTC_OUTPUT_POLARITY_LOW)) |
|||
|
|||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ |
|||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) |
|||
|
|||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) |
|||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) |
|||
|
|||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) |
|||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) |
|||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) |
|||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) |
|||
|
|||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ |
|||
((PM) == RTC_HOURFORMAT12_PM)) |
|||
|
|||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ |
|||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ |
|||
((SAVE) == RTC_DAYLIGHTSAVING_NONE)) |
|||
|
|||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ |
|||
((OPERATION) == RTC_STOREOPERATION_SET)) |
|||
|
|||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) |
|||
|
|||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) |
|||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) |
|||
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) |
|||
|
|||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) |
|||
|
|||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) |
|||
|
|||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ |
|||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) |
|||
|
|||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ |
|||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) |
|||
|
|||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U) |
|||
|
|||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) |
|||
|
|||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) |
|||
|
|||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ |
|||
((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); |
|||
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); |
|||
uint8_t RTC_ByteToBcd2(uint8_t number); |
|||
uint8_t RTC_Bcd2ToByte(uint8_t number); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_RTC_H */ |
|||
File diff suppressed because it is too large
@ -0,0 +1,895 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_sai.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SAI HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_SAI_H |
|||
#define __STM32F4xx_HAL_SAI_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
|||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \ |
|||
defined(STM32F423xx) |
|||
|
|||
/** @addtogroup SAI
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SAI_Exported_Types SAI Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ |
|||
HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ |
|||
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ |
|||
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ |
|||
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ |
|||
HAL_SAI_STATE_TIMEOUT = 0x03U, /*!< SAI timeout state */ |
|||
HAL_SAI_STATE_ERROR = 0x04U /*!< SAI error state */ |
|||
} HAL_SAI_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief SAI Callback prototype |
|||
*/ |
|||
typedef void (*SAIcallback)(void); |
|||
|
|||
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
|
|||
* @brief SAI Init Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
|
|||
This parameter can be a value of @ref SAI_Block_Mode */ |
|||
|
|||
uint32_t Synchro; /*!< Specifies SAI Block synchronization
|
|||
This parameter can be a value of @ref SAI_Block_Synchronization */ |
|||
|
|||
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
|
|||
for BlockA and BlockB |
|||
This parameter can be a value of @ref SAI_Block_SyncExt |
|||
@note: If both audio blocks of same SAI are used, this parameter has |
|||
to be set to the same value for each audio block */ |
|||
|
|||
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
|
|||
This parameter can be a value of @ref SAI_Block_Output_Drive |
|||
@note this value has to be set before enabling the audio block |
|||
but after the audio block configuration. */ |
|||
|
|||
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
|
|||
This parameter can be a value of @ref SAI_Block_NoDivider |
|||
@note If bit NODIV in the SAI_xCR1 register is cleared, the frame length |
|||
should be aligned to a number equal to a power of 2, from 8 to 256. |
|||
If bit NODIV in the SAI_xCR1 register is set, the frame length can |
|||
take any of the values without constraint since the input clock of |
|||
the audio block should be equal to the bit clock. |
|||
There is no MCLK_x clock which can be output. */ |
|||
|
|||
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
|
|||
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ |
|||
|
|||
uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
|
|||
This parameter is not used for STM32F446xx devices. */ |
|||
|
|||
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
|
|||
This parameter can be a value of @ref SAI_Audio_Frequency */ |
|||
|
|||
uint32_t Mckdiv; /*!< Specifies the master clock divider.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 15. |
|||
@note This parameter is used only if AudioFrequency is set to |
|||
SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ |
|||
|
|||
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
|
|||
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ |
|||
|
|||
uint32_t CompandingMode; /*!< Specifies the companding mode type.
|
|||
This parameter can be a value of @ref SAI_Block_Companding_Mode */ |
|||
|
|||
uint32_t TriState; /*!< Specifies the companding mode type.
|
|||
This parameter can be a value of @ref SAI_TRIState_Management */ |
|||
|
|||
/* This part of the structure is automatically filled if your are using the high level initialisation
|
|||
function HAL_SAI_InitProtocol */ |
|||
|
|||
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
|
|||
This parameter can be a value of @ref SAI_Block_Protocol */ |
|||
|
|||
uint32_t DataSize; /*!< Specifies the SAI Block data size.
|
|||
This parameter can be a value of @ref SAI_Block_Data_Size */ |
|||
|
|||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
|||
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ |
|||
|
|||
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
|
|||
This parameter can be a value of @ref SAI_Block_Clock_Strobing */ |
|||
} SAI_InitTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
|
|||
* @brief SAI Frame Init structure definition |
|||
* @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
|
|||
This parameter must be a number between Min_Data = 8 and Max_Data = 256. |
|||
@note If master clock MCLK_x pin is declared as an output, the frame length |
|||
should be aligned to a number equal to power of 2 in order to keep |
|||
in an audio frame, an integer number of MCLK pulses by bit Clock. */ |
|||
|
|||
uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
|
|||
This Parameter specifies the length in number of bit clock (SCK + 1) |
|||
of the active level of FS signal in audio frame. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ |
|||
|
|||
uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
|
|||
This parameter can be a value of @ref SAI_Block_FS_Definition */ |
|||
|
|||
uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
|
|||
This parameter can be a value of @ref SAI_Block_FS_Polarity */ |
|||
|
|||
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
|
|||
This parameter can be a value of @ref SAI_Block_FS_Offset */ |
|||
} SAI_FrameInitTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
|
|||
* @brief SAI Block Slot Init Structure definition |
|||
* @note For SPDIF protocol, these parameters are not used (set by hardware). |
|||
* @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ |
|||
|
|||
uint32_t SlotSize; /*!< Specifies the Slot Size.
|
|||
This parameter can be a value of @ref SAI_Block_Slot_Size */ |
|||
|
|||
uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
|||
|
|||
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
|
|||
This parameter can be a value of @ref SAI_Block_Slot_Active */ |
|||
} SAI_SlotInitTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
|
|||
* @brief SAI handle Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct __SAI_HandleTypeDef |
|||
{ |
|||
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ |
|||
|
|||
SAI_InitTypeDef Init; /*!< SAI communication parameters */ |
|||
|
|||
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ |
|||
|
|||
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ |
|||
|
|||
uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ |
|||
|
|||
uint16_t XferSize; /*!< SAI transfer size */ |
|||
|
|||
uint16_t XferCount; /*!< SAI transfer counter */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ |
|||
|
|||
SAIcallback mutecallback;/*!< SAI mute callback */ |
|||
|
|||
void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< SAI locking object */ |
|||
|
|||
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< SAI Error code */ |
|||
|
|||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) |
|||
void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ |
|||
void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ |
|||
void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ |
|||
void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ |
|||
void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ |
|||
void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ |
|||
void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ |
|||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ |
|||
} SAI_HandleTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief SAI callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ |
|||
HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ |
|||
HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ |
|||
HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ |
|||
HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ |
|||
HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ |
|||
HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ |
|||
} HAL_SAI_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief SAI callback pointer definition |
|||
*/ |
|||
typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); |
|||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SAI_Exported_Constants SAI Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Error_Code SAI Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ |
|||
#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ |
|||
#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ |
|||
#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ |
|||
#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ |
|||
#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ |
|||
#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ |
|||
#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ |
|||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) |
|||
#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ |
|||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
|
|||
* @{ |
|||
*/ |
|||
#define SAI_SYNCEXT_DISABLE 0U |
|||
#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U |
|||
#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Protocol SAI Supported protocol
|
|||
* @{ |
|||
*/ |
|||
#define SAI_I2S_STANDARD 0U |
|||
#define SAI_I2S_MSBJUSTIFIED 1U |
|||
#define SAI_I2S_LSBJUSTIFIED 2U |
|||
#define SAI_PCM_LONG 3U |
|||
#define SAI_PCM_SHORT 4U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
|
|||
* @{ |
|||
*/ |
|||
#define SAI_PROTOCOL_DATASIZE_16BIT 0U |
|||
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U |
|||
#define SAI_PROTOCOL_DATASIZE_24BIT 2U |
|||
#define SAI_PROTOCOL_DATASIZE_32BIT 3U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
|
|||
* @{ |
|||
*/ |
|||
#define SAI_AUDIO_FREQUENCY_192K 192000U |
|||
#define SAI_AUDIO_FREQUENCY_96K 96000U |
|||
#define SAI_AUDIO_FREQUENCY_48K 48000U |
|||
#define SAI_AUDIO_FREQUENCY_44K 44100U |
|||
#define SAI_AUDIO_FREQUENCY_32K 32000U |
|||
#define SAI_AUDIO_FREQUENCY_22K 22050U |
|||
#define SAI_AUDIO_FREQUENCY_16K 16000U |
|||
#define SAI_AUDIO_FREQUENCY_11K 11025U |
|||
#define SAI_AUDIO_FREQUENCY_8K 8000U |
|||
#define SAI_AUDIO_FREQUENCY_MCKDIV 0U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Mode SAI Block Mode
|
|||
* @{ |
|||
*/ |
|||
#define SAI_MODEMASTER_TX 0x00000000U |
|||
#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) |
|||
#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) |
|||
#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Protocol SAI Block Protocol
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FREE_PROTOCOL 0x00000000U |
|||
#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) |
|||
#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
|
|||
* @{ |
|||
*/ |
|||
#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) |
|||
#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) |
|||
#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) |
|||
#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) |
|||
#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) |
|||
#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FIRSTBIT_MSB 0x00000000U |
|||
#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
|
|||
* @{ |
|||
*/ |
|||
#define SAI_CLOCKSTROBING_FALLINGEDGE 0U |
|||
#define SAI_CLOCKSTROBING_RISINGEDGE 1U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
|
|||
* @{ |
|||
*/ |
|||
#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ |
|||
#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ |
|||
#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ |
|||
#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
|
|||
* @{ |
|||
*/ |
|||
#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U |
|||
#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
|
|||
* @{ |
|||
*/ |
|||
#define SAI_MASTERDIVIDER_ENABLE 0x00000000U |
|||
#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FS_STARTFRAME 0x00000000U |
|||
#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FS_ACTIVE_LOW 0x00000000U |
|||
#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FS_FIRSTBIT 0x00000000U |
|||
#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
|
|||
* @{ |
|||
*/ |
|||
#define SAI_SLOTSIZE_DATASIZE 0x00000000U |
|||
#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) |
|||
#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
|
|||
* @{ |
|||
*/ |
|||
#define SAI_SLOT_NOTACTIVE 0x00000000U |
|||
#define SAI_SLOTACTIVE_0 0x00000001U |
|||
#define SAI_SLOTACTIVE_1 0x00000002U |
|||
#define SAI_SLOTACTIVE_2 0x00000004U |
|||
#define SAI_SLOTACTIVE_3 0x00000008U |
|||
#define SAI_SLOTACTIVE_4 0x00000010U |
|||
#define SAI_SLOTACTIVE_5 0x00000020U |
|||
#define SAI_SLOTACTIVE_6 0x00000040U |
|||
#define SAI_SLOTACTIVE_7 0x00000080U |
|||
#define SAI_SLOTACTIVE_8 0x00000100U |
|||
#define SAI_SLOTACTIVE_9 0x00000200U |
|||
#define SAI_SLOTACTIVE_10 0x00000400U |
|||
#define SAI_SLOTACTIVE_11 0x00000800U |
|||
#define SAI_SLOTACTIVE_12 0x00001000U |
|||
#define SAI_SLOTACTIVE_13 0x00002000U |
|||
#define SAI_SLOTACTIVE_14 0x00004000U |
|||
#define SAI_SLOTACTIVE_15 0x00008000U |
|||
#define SAI_SLOTACTIVE_ALL 0x0000FFFFU |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
|
|||
* @{ |
|||
*/ |
|||
#define SAI_STEREOMODE 0x00000000U |
|||
#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_TRIState_Management SAI TRIState Management
|
|||
* @{ |
|||
*/ |
|||
#define SAI_OUTPUT_NOTRELEASED 0x00000000U |
|||
#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U |
|||
#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) |
|||
#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) |
|||
#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) |
|||
#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
|
|||
* @{ |
|||
*/ |
|||
#define SAI_NOCOMPANDING 0x00000000U |
|||
#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) |
|||
#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) |
|||
#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) |
|||
#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
|
|||
* @{ |
|||
*/ |
|||
#define SAI_ZERO_VALUE 0x00000000U |
|||
#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
|
|||
* @{ |
|||
*/ |
|||
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) |
|||
#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) |
|||
#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) |
|||
#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) |
|||
#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) |
|||
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) |
|||
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) |
|||
#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) |
|||
#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) |
|||
#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) |
|||
#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) |
|||
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) |
|||
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
|
|||
* @{ |
|||
*/ |
|||
#define SAI_FIFOSTATUS_EMPTY 0x00000000U |
|||
#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U |
|||
#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U |
|||
#define SAI_FIFOSTATUS_HALFFULL 0x00030000U |
|||
#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U |
|||
#define SAI_FIFOSTATUS_FULL 0x00050000U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup SAI_Exported_Macros SAI Exported Macros
|
|||
* @brief macros to handle interrupts and specific configurations |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SAI handle state
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_SAI_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0U) |
|||
#else |
|||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) |
|||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Enable or disable the specified SAI interrupts.
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable |
|||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable |
|||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable |
|||
* @arg SAI_IT_FREQ: FIFO request interrupt enable |
|||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable |
|||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable |
|||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) |
|||
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) |
|||
|
|||
/** @brief Check if the specified SAI interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral. |
|||
* @param __INTERRUPT__ specifies the SAI interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable |
|||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable |
|||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable |
|||
* @arg SAI_IT_FREQ: FIFO request interrupt enable |
|||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable |
|||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable |
|||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable |
|||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Check whether the specified SAI flag is set or not.
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag. |
|||
* @arg SAI_FLAG_MUTEDET: Mute detection flag. |
|||
* @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag. |
|||
* @arg SAI_FLAG_FREQ: FIFO request flag. |
|||
* @arg SAI_FLAG_CNRDY: Codec not ready flag. |
|||
* @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. |
|||
* @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clear the specified SAI pending flag.
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun |
|||
* @arg SAI_FLAG_MUTEDET: Clear Mute detection |
|||
* @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration |
|||
* @arg SAI_FLAG_FREQ: Clear FIFO request |
|||
* @arg SAI_FLAG_CNRDY: Clear Codec not ready |
|||
* @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection |
|||
* @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) |
|||
|
|||
/** @brief Enable SAI
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) |
|||
|
|||
/** @brief Disable SAI
|
|||
* @param __HANDLE__ specifies the SAI Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include HAL SAI Extension module */ |
|||
#include "stm32f4xx_hal_sai_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SAI_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions **********************************/ |
|||
/** @addtogroup SAI_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); |
|||
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); |
|||
HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); |
|||
|
|||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) |
|||
/* SAI callbacks register/unregister functions ********************************/ |
|||
HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, |
|||
HAL_SAI_CallbackIDTypeDef CallbackID, |
|||
pSAI_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, |
|||
HAL_SAI_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* I/O operation functions *****************************************************/ |
|||
/** @addtogroup SAI_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
|
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); |
|||
|
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai); |
|||
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai); |
|||
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai); |
|||
|
|||
/* Abort function */ |
|||
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai); |
|||
|
|||
/* Mute management */ |
|||
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val); |
|||
HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai); |
|||
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter); |
|||
HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai); |
|||
|
|||
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
|||
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai); |
|||
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SAI_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ************************************************/ |
|||
HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); |
|||
uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @addtogroup SAI_Private_Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ |
|||
((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ |
|||
((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) |
|||
|
|||
#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ |
|||
((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ |
|||
((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\ |
|||
((PROTOCOL) == SAI_PCM_LONG) ||\ |
|||
((PROTOCOL) == SAI_PCM_SHORT)) |
|||
|
|||
#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\ |
|||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\ |
|||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ |
|||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) |
|||
|
|||
#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ |
|||
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ |
|||
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ |
|||
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ |
|||
((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) |
|||
|
|||
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ |
|||
((MODE) == SAI_MODEMASTER_RX) || \ |
|||
((MODE) == SAI_MODESLAVE_TX) || \ |
|||
((MODE) == SAI_MODESLAVE_RX)) |
|||
|
|||
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ |
|||
((PROTOCOL) == SAI_AC97_PROTOCOL) || \ |
|||
((PROTOCOL) == SAI_SPDIF_PROTOCOL)) |
|||
|
|||
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ |
|||
((DATASIZE) == SAI_DATASIZE_10) || \ |
|||
((DATASIZE) == SAI_DATASIZE_16) || \ |
|||
((DATASIZE) == SAI_DATASIZE_20) || \ |
|||
((DATASIZE) == SAI_DATASIZE_24) || \ |
|||
((DATASIZE) == SAI_DATASIZE_32)) |
|||
|
|||
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \ |
|||
((BIT) == SAI_FIRSTBIT_LSB)) |
|||
|
|||
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ |
|||
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) |
|||
|
|||
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ |
|||
((SYNCHRO) == SAI_SYNCHRONOUS) || \ |
|||
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\ |
|||
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) |
|||
|
|||
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ |
|||
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) |
|||
|
|||
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ |
|||
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) |
|||
|
|||
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) |
|||
|
|||
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ |
|||
((VALUE) == SAI_LAST_SENT_VALUE)) |
|||
|
|||
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ |
|||
((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ |
|||
((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ |
|||
((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ |
|||
((MODE) == SAI_ALAW_2CPL_COMPANDING)) |
|||
|
|||
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ |
|||
((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ |
|||
((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ |
|||
((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ |
|||
((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) |
|||
|
|||
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ |
|||
((STATE) == SAI_OUTPUT_RELEASED)) |
|||
|
|||
#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ |
|||
((MODE) == SAI_STEREOMODE)) |
|||
|
|||
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) |
|||
|
|||
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) |
|||
|
|||
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ |
|||
((SIZE) == SAI_SLOTSIZE_16B) || \ |
|||
((SIZE) == SAI_SLOTSIZE_32B)) |
|||
|
|||
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) |
|||
|
|||
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ |
|||
((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) |
|||
|
|||
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ |
|||
((POLARITY) == SAI_FS_ACTIVE_HIGH)) |
|||
|
|||
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ |
|||
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) |
|||
|
|||
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) |
|||
|
|||
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) |
|||
|
|||
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup SAI_Private_Functions SAI Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_SAI_H */ |
|||
|
|||
@ -0,0 +1,114 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_sai_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SAI Extension HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_SAI_EX_H |
|||
#define __STM32F4xx_HAL_SAI_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SAIEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
|||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \ |
|||
defined(STM32F423xx) |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SAI_Clock_Source SAI Clock Source
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F413xx) || defined(STM32F423xx) |
|||
#define SAI_CLKSOURCE_PLLI2S 0x00000000U |
|||
#define SAI_CLKSOURCE_EXT 0x00100000U |
|||
#define SAI_CLKSOURCE_PLLR 0x00200000U |
|||
#define SAI_CLKSOURCE_HS 0x00300000U |
|||
#else |
|||
#define SAI_CLKSOURCE_PLLSAI 0x00000000U |
|||
#define SAI_CLKSOURCE_PLLI2S 0x00100000U |
|||
#define SAI_CLKSOURCE_EXT 0x00200000U |
|||
#define SAI_CLKSOURCE_NA 0x00400000U /*!< No applicable for STM32F446xx */ |
|||
#endif |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SAIEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SAIEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Extended features functions ************************************************/ |
|||
void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai); |
|||
uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
#if defined(STM32F413xx) || defined(STM32F423xx) |
|||
#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\ |
|||
((SOURCE) == SAI_CLKSOURCE_EXT)||\ |
|||
((SOURCE) == SAI_CLKSOURCE_PLLR)||\ |
|||
((SOURCE) == SAI_CLKSOURCE_HS)) |
|||
#else |
|||
#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\ |
|||
((SOURCE) == SAI_CLKSOURCE_EXT)||\ |
|||
((SOURCE) == SAI_CLKSOURCE_PLLI2S)||\ |
|||
((SOURCE) == SAI_CLKSOURCE_NA)) |
|||
#endif |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_SAI_EX_H */ |
|||
|
|||
@ -0,0 +1,758 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_sd.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SD HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_SD_H |
|||
#define STM32F4xx_HAL_SD_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(SDIO) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_ll_sdmmc.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SD SD
|
|||
* @brief SD HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_Types SD Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */ |
|||
HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */ |
|||
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */ |
|||
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ |
|||
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ |
|||
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */ |
|||
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */ |
|||
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ |
|||
}HAL_SD_StateTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
|
|||
* @{ |
|||
*/ |
|||
typedef uint32_t HAL_SD_CardStateTypeDef; |
|||
|
|||
#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ |
|||
#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ |
|||
#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ |
|||
#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ |
|||
#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ |
|||
#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ |
|||
#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ |
|||
#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ |
|||
#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
|
|||
* @{ |
|||
*/ |
|||
#define SD_InitTypeDef SDIO_InitTypeDef |
|||
#define SD_TypeDef SDIO_TypeDef |
|||
|
|||
/**
|
|||
* @brief SD Card Information Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t CardType; /*!< Specifies the card Type */ |
|||
|
|||
uint32_t CardVersion; /*!< Specifies the card version */ |
|||
|
|||
uint32_t Class; /*!< Specifies the class of the card class */ |
|||
|
|||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ |
|||
|
|||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ |
|||
|
|||
uint32_t BlockSize; /*!< Specifies one block size in bytes */ |
|||
|
|||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ |
|||
|
|||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ |
|||
|
|||
}HAL_SD_CardInfoTypeDef; |
|||
|
|||
/**
|
|||
* @brief SD handle Structure definition |
|||
*/ |
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
typedef struct __SD_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
{ |
|||
SD_TypeDef *Instance; /*!< SD registers base address */ |
|||
|
|||
SD_InitTypeDef Init; /*!< SD required parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< SD locking object */ |
|||
|
|||
uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ |
|||
|
|||
uint32_t TxXferSize; /*!< SD Tx Transfer size */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ |
|||
|
|||
uint32_t RxXferSize; /*!< SD Rx Transfer size */ |
|||
|
|||
__IO uint32_t Context; /*!< SD transfer context */ |
|||
|
|||
__IO HAL_SD_StateTypeDef State; /*!< SD card State */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< SD Card Error codes */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ |
|||
|
|||
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ |
|||
|
|||
uint32_t CSD[4]; /*!< SD card specific data table */ |
|||
|
|||
uint32_t CID[4]; /*!< SD card identification number table */ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); |
|||
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); |
|||
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); |
|||
void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); |
|||
|
|||
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); |
|||
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
}SD_HandleTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t CSDStruct; /*!< CSD structure */ |
|||
__IO uint8_t SysSpecVersion; /*!< System specification version */ |
|||
__IO uint8_t Reserved1; /*!< Reserved */ |
|||
__IO uint8_t TAAC; /*!< Data read access time 1 */ |
|||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ |
|||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ |
|||
__IO uint16_t CardComdClasses; /*!< Card command classes */ |
|||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */ |
|||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ |
|||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ |
|||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ |
|||
__IO uint8_t DSRImpl; /*!< DSR implemented */ |
|||
__IO uint8_t Reserved2; /*!< Reserved */ |
|||
__IO uint32_t DeviceSize; /*!< Device Size */ |
|||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ |
|||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ |
|||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ |
|||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ |
|||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ |
|||
__IO uint8_t EraseGrSize; /*!< Erase group size */ |
|||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ |
|||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */ |
|||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ |
|||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ |
|||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */ |
|||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ |
|||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ |
|||
__IO uint8_t Reserved3; /*!< Reserved */ |
|||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */ |
|||
__IO uint8_t FileFormatGroup; /*!< File format group */ |
|||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ |
|||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */ |
|||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */ |
|||
__IO uint8_t FileFormat; /*!< File format */ |
|||
__IO uint8_t ECC; /*!< ECC code */ |
|||
__IO uint8_t CSD_CRC; /*!< CSD CRC */ |
|||
__IO uint8_t Reserved4; /*!< Always 1 */ |
|||
}HAL_SD_CardCSDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */ |
|||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ |
|||
__IO uint32_t ProdName1; /*!< Product Name part1 */ |
|||
__IO uint8_t ProdName2; /*!< Product Name part2 */ |
|||
__IO uint8_t ProdRev; /*!< Product Revision */ |
|||
__IO uint32_t ProdSN; /*!< Product Serial Number */ |
|||
__IO uint8_t Reserved1; /*!< Reserved1 */ |
|||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */ |
|||
__IO uint8_t CID_CRC; /*!< CID CRC */ |
|||
__IO uint8_t Reserved2; /*!< Always 1 */ |
|||
|
|||
}HAL_SD_CardCIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ |
|||
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ |
|||
__IO uint16_t CardType; /*!< Carries information about card type */ |
|||
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ |
|||
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ |
|||
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ |
|||
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ |
|||
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ |
|||
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ |
|||
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ |
|||
|
|||
}HAL_SD_CardStatusTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ |
|||
HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ |
|||
HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ |
|||
HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ |
|||
|
|||
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ |
|||
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ |
|||
}HAL_SD_CallbackIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
|
|||
* @{ |
|||
*/ |
|||
typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_Constants Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
|
|||
* @{ |
|||
*/ |
|||
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ |
|||
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ |
|||
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ |
|||
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ |
|||
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ |
|||
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ |
|||
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ |
|||
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ |
|||
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the |
|||
number of transferred bytes does not match the block length */ |
|||
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ |
|||
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ |
|||
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ |
|||
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock |
|||
command or if there was an attempt to access a locked card */ |
|||
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ |
|||
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ |
|||
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ |
|||
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ |
|||
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ |
|||
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ |
|||
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ |
|||
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ |
|||
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ |
|||
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ |
|||
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out |
|||
of erase sequence command was received */ |
|||
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ |
|||
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ |
|||
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ |
|||
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ |
|||
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ |
|||
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ |
|||
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ |
|||
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ |
|||
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
|
|||
* @{ |
|||
*/ |
|||
#define SD_CONTEXT_NONE 0x00000000U /*!< None */ |
|||
#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ |
|||
#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ |
|||
#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ |
|||
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ |
|||
#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ |
|||
#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
|
|||
* @{ |
|||
*/ |
|||
#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */ |
|||
#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ |
|||
#define CARD_SECURED 0x00000003U |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
|
|||
* @{ |
|||
*/ |
|||
#define CARD_V1_X 0x00000000U |
|||
#define CARD_V2_X 0x00000001U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_macros SD Exported Macros
|
|||
* @brief macros to handle interrupts and specific clock configurations |
|||
* @{ |
|||
*/ |
|||
/** @brief Reset SD handle state.
|
|||
* @param __HANDLE__ : SD handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_SD_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable the SD device. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Disable the SD device. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Enable the SDMMC DMA transfer. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Disable the SDMMC DMA transfer. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) |
|||
|
|||
/**
|
|||
* @brief Enable the SD device interrupt. |
|||
* @param __HANDLE__: SD Handle |
|||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the SD device interrupt. |
|||
* @param __HANDLE__: SD Handle |
|||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified SD flag is set or not. |
|||
* @param __HANDLE__: SD Handle |
|||
* @param __FLAG__: specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress |
|||
* @arg SDIO_FLAG_TXACT: Data transmit in progress |
|||
* @arg SDIO_FLAG_RXACT: Data receive in progress |
|||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
|||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
|||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
|||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
|||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
|||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
|||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
|||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
|||
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received |
|||
* @retval The new state of SD FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the SD's pending flags. |
|||
* @param __HANDLE__: SD Handle |
|||
* @param __FLAG__: specifies the flag to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified SD interrupt has occurred or not. |
|||
* @param __HANDLE__: SD Handle |
|||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @retval The new state of SD IT (SET or RESET). |
|||
*/ |
|||
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Clear the SD's interrupt pending bits. |
|||
* @param __HANDLE__: SD Handle |
|||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_Functions SD Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); |
|||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); |
|||
/* Non-Blocking mode: IT */ |
|||
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
|
|||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); |
|||
|
|||
/* Callback in non blocking modes (DMA) */ |
|||
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
/* SD callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId); |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); |
|||
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); |
|||
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); |
|||
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); |
|||
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
|
|||
* @{ |
|||
*/ |
|||
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); |
|||
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Types SD Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Defines SD Private Defines
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Variables SD Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Constants SD Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Macros SD Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Functions SD Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* SDIO */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_SD_H */ |
|||
@ -0,0 +1,238 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_sdram.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SDRAM HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_SDRAM_H |
|||
#define STM32F4xx_HAL_SDRAM_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMC_Bank5_6) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_ll_fmc.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SDRAM
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported typedef ----------------------------------------------------------*/ |
|||
|
|||
/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL SDRAM State structure definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ |
|||
HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ |
|||
HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ |
|||
HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ |
|||
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ |
|||
HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ |
|||
|
|||
} HAL_SDRAM_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief SDRAM handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
|||
typedef struct __SDRAM_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
|||
{ |
|||
FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ |
|||
|
|||
__IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< SDRAM locking object */ |
|||
|
|||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
|||
|
|||
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
|||
void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ |
|||
void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ |
|||
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ |
|||
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ |
|||
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
|||
} SDRAM_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL SDRAM Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ |
|||
HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ |
|||
HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ |
|||
HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ |
|||
HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ |
|||
} HAL_SDRAM_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SDRAM Callback pointer definition |
|||
*/ |
|||
typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); |
|||
typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); |
|||
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SDRAM handle state
|
|||
* @param __HANDLE__ specifies the SDRAM handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) |
|||
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SDRAM_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions *********************************/ |
|||
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); |
|||
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); |
|||
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); |
|||
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); |
|||
|
|||
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); |
|||
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); |
|||
void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
|||
void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SDRAM_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ****************************************************/ |
|||
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
|
|||
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
|
|||
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) |
|||
/* SDRAM callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, |
|||
pSDRAM_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); |
|||
HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, |
|||
pSDRAM_DmaCallbackTypeDef pCallback); |
|||
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SDRAM_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* SDRAM Control functions *****************************************************/ |
|||
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); |
|||
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); |
|||
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); |
|||
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); |
|||
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SDRAM_Exported_Functions_Group4
|
|||
* @{ |
|||
*/ |
|||
/* SDRAM State functions ********************************************************/ |
|||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMC_Bank5_6 */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_SDRAM_H */ |
|||
@ -0,0 +1,755 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_smartcard.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SMARTCARD HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_SMARTCARD_H |
|||
#define __STM32F4xx_HAL_SMARTCARD_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SMARTCARD
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief SMARTCARD Init Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
|
|||
The baud rate is computed using the following formula: |
|||
- IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate))) |
|||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ |
|||
|
|||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
|||
This parameter can be a value of @ref SMARTCARD_Word_Length */ |
|||
|
|||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
|||
This parameter can be a value of @ref SMARTCARD_Stop_Bits */ |
|||
|
|||
uint32_t Parity; /*!< Specifies the parity mode.
|
|||
This parameter can be a value of @ref SMARTCARD_Parity |
|||
@note When parity is enabled, the computed parity is inserted |
|||
at the MSB position of the transmitted data (9th bit when |
|||
the word length is set to 9 data bits; 8th bit when the |
|||
word length is set to 8 data bits).*/ |
|||
|
|||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
|||
This parameter can be a value of @ref SMARTCARD_Mode */ |
|||
|
|||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
|||
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ |
|||
|
|||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
|||
This parameter can be a value of @ref SMARTCARD_Clock_Phase */ |
|||
|
|||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
|||
data bit (MSB) has to be output on the SCLK pin in synchronous mode. |
|||
This parameter can be a value of @ref SMARTCARD_Last_Bit */ |
|||
|
|||
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
|
|||
to provide the smartcard clock. The value given in the register (5 significant bits) |
|||
is multiplied by 2 to give the division factor of the source clock frequency. |
|||
This parameter can be a value of @ref SMARTCARD_Prescaler */ |
|||
|
|||
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ |
|||
|
|||
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
|
|||
This parameter can be a value of @ref SMARTCARD_NACK_State */ |
|||
}SMARTCARD_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SMARTCARD State structures definition |
|||
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. |
|||
* - gState contains SMARTCARD state information related to global Handle management |
|||
* and also information related to Tx operations. |
|||
* gState value coding follow below described bitmap : |
|||
* b7-b6 Error information |
|||
* 00 : No Error |
|||
* 01 : (Not Used) |
|||
* 10 : Timeout |
|||
* 11 : Error |
|||
* b5 IP initialization status |
|||
* 0 : Reset (IP not initialized) |
|||
* 1 : Init done (IP initialized. HAL SMARTCARD Init function already called) |
|||
* b4-b3 (not used) |
|||
* xx : Should be set to 00 |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (IP busy with some configuration or internal operations) |
|||
* b1 (not used) |
|||
* x : Should be set to 0 |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* - RxState contains information related to Rx operations. |
|||
* RxState value coding follow below described bitmap : |
|||
* b7-b6 (not used) |
|||
* xx : Should be set to 00 |
|||
* b5 IP initialization status |
|||
* 0 : Reset (IP not initialized) |
|||
* 1 : Init done (IP initialized) |
|||
* b4-b2 (not used) |
|||
* xxx : Should be set to 000 |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 (not used) |
|||
* x : Should be set to 0. |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
|||
Value is allowed for gState and RxState */ |
|||
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
|||
Value is allowed for gState and RxState */ |
|||
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
|||
Value is allowed for gState only */ |
|||
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
|||
Value is allowed for gState only */ |
|||
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
|||
Value is allowed for RxState only */ |
|||
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
|||
Not to be used for neither gState nor RxState. |
|||
Value is result of combination (Or) between gState and RxState values */ |
|||
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
|||
Value is allowed for gState only */ |
|||
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
|
|||
Value is allowed for gState only */ |
|||
}HAL_SMARTCARD_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief SMARTCARD handle Structure definition |
|||
*/ |
|||
typedef struct __SMARTCARD_HandleTypeDef |
|||
{ |
|||
USART_TypeDef *Instance; /*!< USART registers base address */ |
|||
|
|||
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ |
|||
|
|||
const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ |
|||
|
|||
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ |
|||
|
|||
__IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ |
|||
|
|||
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
|
|||
and also related to Tx operations. |
|||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ |
|||
|
|||
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
|
|||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< SmartCard Error code */ |
|||
|
|||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) |
|||
void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Tx Complete Callback */ |
|||
|
|||
void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Rx Complete Callback */ |
|||
|
|||
void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Error Callback */ |
|||
|
|||
void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Complete Callback */ |
|||
|
|||
void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */ |
|||
|
|||
void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Receive Complete Callback */ |
|||
|
|||
void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp Init callback */ |
|||
|
|||
void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp DeInit callback */ |
|||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ |
|||
|
|||
} SMARTCARD_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL SMARTCARD Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */ |
|||
HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */ |
|||
HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */ |
|||
HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */ |
|||
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */ |
|||
HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */ |
|||
|
|||
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */ |
|||
HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */ |
|||
|
|||
} HAL_SMARTCARD_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SMARTCARD Callback pointer definition |
|||
*/ |
|||
typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc); /*!< pointer to an SMARTCARD callback function */ |
|||
|
|||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */ |
|||
#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */ |
|||
#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */ |
|||
#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */ |
|||
#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
|||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) |
|||
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) |
|||
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) |
|||
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) |
|||
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) |
|||
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_POLARITY_LOW 0x00000000U |
|||
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_PHASE_1EDGE 0x00000000U |
|||
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_LASTBIT_DISABLE 0x00000000U |
|||
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) |
|||
#define SMARTCARD_NACK_DISABLE 0x00000000U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) |
|||
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */ |
|||
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SmartCard_Flags SMARTCARD Flags
|
|||
* Elements values convention: 0xXXXX |
|||
* - 0xXXXX : Flag mask in the SR register |
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE) |
|||
#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC) |
|||
#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE) |
|||
#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE) |
|||
#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE) |
|||
#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE) |
|||
#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE) |
|||
#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
|
|||
* Elements values convention: 0xY000XXXX |
|||
* - XXXX : Interrupt mask in the Y register |
|||
* - Y : Interrupt source register (2bits) |
|||
* - 01: CR1 register |
|||
* - 11: CR3 register |
|||
* @{ |
|||
*/ |
|||
#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) |
|||
#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) |
|||
#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) |
|||
#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) |
|||
#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) |
|||
#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SMARTCARD handle gstate & RxState
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 |
|||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0U) |
|||
#else |
|||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ |
|||
} while(0U) |
|||
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Flush the Smartcard DR register
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) |
|||
|
|||
/** @brief Check whether the specified Smartcard flag is set or not.
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag |
|||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag |
|||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag |
|||
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag |
|||
* @arg SMARTCARD_FLAG_ORE: Overrun Error flag |
|||
* @arg SMARTCARD_FLAG_NE: Noise Error flag |
|||
* @arg SMARTCARD_FLAG_FE: Framing Error flag |
|||
* @arg SMARTCARD_FLAG_PE: Parity Error flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clear the specified Smartcard pending flags.
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag. |
|||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag. |
|||
* |
|||
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun |
|||
* error) flags are cleared by software sequence: a read operation to |
|||
* USART_SR register followed by a read operation to USART_DR register. |
|||
* @note RXNE flag can be also cleared by a read to the USART_DR register. |
|||
* @note TC flag can be also cleared by software sequence: a read operation to |
|||
* USART_SR register followed by a write operation to USART_DR register. |
|||
* @note TXE flag is cleared only by a write to the USART_DR register. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
|||
|
|||
/** @brief Clear the SMARTCARD PE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR; \ |
|||
tmpreg = (__HANDLE__)->Instance->DR; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Clear the SMARTCARD FE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the SMARTCARD NE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the SMARTCARD ORE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the SMARTCARD IDLE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Enable the specified SmartCard interrupt.
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt |
|||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt |
|||
* @arg SMARTCARD_IT_PE: Parity Error interrupt |
|||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK))) |
|||
|
|||
/** @brief Disable the specified SmartCard interrupt.
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt |
|||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt |
|||
* @arg SMARTCARD_IT_PE: Parity Error interrupt |
|||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) |
|||
|
|||
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
|||
* @param __HANDLE__ specifies the SmartCard Handle. |
|||
* @param __IT__ specifies the SMARTCARD interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt |
|||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt |
|||
* @arg SMARTCARD_IT_ERR: Error interrupt |
|||
* @arg SMARTCARD_IT_PE: Parity Error interrupt |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) |
|||
|
|||
/** @brief Macro to enable the SMARTCARD's one bit sample method
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) |
|||
|
|||
/** @brief Macro to disable the SMARTCARD's one bit sample method
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) |
|||
|
|||
/** @brief Enable the USART associated to the SMARTCARD Handle
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
|||
|
|||
/** @brief Disable the USART associated to the SMARTCARD Handle
|
|||
* @param __HANDLE__ specifies the SMARTCARD Handle. |
|||
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
|||
|
|||
/** @brief Macros to enable the SmartCard DMA request.
|
|||
* @param __HANDLE__ specifies the SmartCard Handle. |
|||
* @param __REQUEST__ specifies the SmartCard DMA request. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request |
|||
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__)) |
|||
|
|||
/** @brief Macros to disable the SmartCard DMA request.
|
|||
* @param __HANDLE__ specifies the SmartCard Handle. |
|||
* @param __REQUEST__ specifies the SmartCard DMA request. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request |
|||
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SMARTCARD_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SMARTCARD_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); |
|||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SMARTCARD_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *******************************************************/ |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); |
|||
/* Transfer Abort functions */ |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc); |
|||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc); |
|||
|
|||
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc); |
|||
void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SMARTCARD_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions **************************************************/ |
|||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc); |
|||
uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief SMARTCARD interruptions flag mask
|
|||
* |
|||
*/ |
|||
#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ |
|||
USART_CR1_IDLEIE | USART_CR3_EIE ) |
|||
|
|||
#define SMARTCARD_CR1_REG_INDEX 1U |
|||
#define SMARTCARD_CR3_REG_INDEX 3U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros --------------------------------------------------------*/ |
|||
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) |
|||
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ |
|||
((STOPBITS) == SMARTCARD_STOPBITS_1_5)) |
|||
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ |
|||
((PARITY) == SMARTCARD_PARITY_ODD)) |
|||
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U)) |
|||
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) |
|||
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) |
|||
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ |
|||
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) |
|||
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \ |
|||
((NACK) == SMARTCARD_NACK_DISABLE)) |
|||
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U) |
|||
|
|||
#define SMARTCARD_DIV(__PCLK__, __BAUD__) ((uint32_t)((((uint64_t)(__PCLK__))*25U)/(4U*((uint64_t)(__BAUD__))))) |
|||
#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U) |
|||
#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U) |
|||
/* SMARTCARD BRR = mantissa + overflow + fraction
|
|||
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */ |
|||
#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \ |
|||
(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \ |
|||
(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_SMARTCARD_H */ |
|||
|
|||
@ -0,0 +1,731 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_smbus.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SMBUS HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_SMBUS_H |
|||
#define __STM32F4xx_HAL_SMBUS_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SMBUS
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief SMBUS Configuration Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
|||
This parameter must be set to a value lower than 100kHz */ |
|||
|
|||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
|||
This parameter can be a value of @ref SMBUS_Analog_Filter */ |
|||
|
|||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
|||
This parameter can be a 7-bit or 10-bit address. */ |
|||
|
|||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
|||
This parameter can be a value of @ref SMBUS_addressing_mode */ |
|||
|
|||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
|||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
|||
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is
|
|||
selected. This parameter can be a 7-bit address. */ |
|||
|
|||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
|||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode */ |
|||
|
|||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
|||
This parameter can be a value of @ref SMBUS_nostretch_mode */ |
|||
|
|||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
|||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
|||
|
|||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
|||
This parameter can be a value of @ref SMBUS_peripheral_mode */ |
|||
|
|||
} SMBUS_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL State structure definition |
|||
* @note HAL SMBUS State value coding follow below described bitmap : |
|||
* b7-b6 Error information |
|||
* 00 : No Error |
|||
* 01 : Abort (Abort user request on going) |
|||
* 10 : Timeout |
|||
* 11 : Error |
|||
* b5 IP initialisation status |
|||
* 0 : Reset (IP not initialized) |
|||
* 1 : Init done (IP initialized and ready to use. HAL SMBUS Init function called) |
|||
* b4 (not used) |
|||
* x : Should be set to 0 |
|||
* b3 |
|||
* 0 : Ready or Busy (No Listen mode ongoing) |
|||
* 1 : Listen (IP in Address Listen Mode) |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (IP busy with some configuration or internal operations) |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
|
|||
HAL_SMBUS_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ |
|||
HAL_SMBUS_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_SMBUS_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ |
|||
HAL_SMBUS_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ |
|||
HAL_SMBUS_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
|||
HAL_SMBUS_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ |
|||
HAL_SMBUS_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
|||
process is ongoing */ |
|||
HAL_SMBUS_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
|||
process is ongoing */ |
|||
HAL_SMBUS_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ |
|||
HAL_SMBUS_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ |
|||
HAL_SMBUS_STATE_ERROR = 0xE0U /*!< Error */ |
|||
} HAL_SMBUS_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL Mode structure definition |
|||
* @note HAL SMBUS Mode value coding follow below described bitmap : |
|||
* b7 (not used) |
|||
* x : Should be set to 0 |
|||
* b6 (not used) |
|||
* x : Should be set to 0 |
|||
* b5 |
|||
* 0 : None |
|||
* 1 : Slave (HAL SMBUS communication is in Slave/Device Mode) |
|||
* b4 |
|||
* 0 : None |
|||
* 1 : Master (HAL SMBUS communication is in Master/Host Mode) |
|||
* b3-b2-b1-b0 (not used) |
|||
* xxxx : Should be set to 0000 |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SMBUS_MODE_NONE = 0x00U, /*!< No SMBUS communication on going */ |
|||
HAL_SMBUS_MODE_MASTER = 0x10U, /*!< SMBUS communication is in Master Mode */ |
|||
HAL_SMBUS_MODE_SLAVE = 0x20U, /*!< SMBUS communication is in Slave Mode */ |
|||
|
|||
} HAL_SMBUS_ModeTypeDef; |
|||
|
|||
/**
|
|||
* @brief SMBUS handle Structure definition |
|||
*/ |
|||
typedef struct __SMBUS_HandleTypeDef |
|||
{ |
|||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
|||
|
|||
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
|||
|
|||
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
|||
|
|||
uint16_t XferSize; /*!< SMBUS transfer size */ |
|||
|
|||
__IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
|||
|
|||
__IO uint32_t XferOptions; /*!< SMBUS transfer options this parameter can
|
|||
be a value of @ref SMBUS_OPTIONS */ |
|||
|
|||
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state and mode
|
|||
context for internal usage */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
|||
|
|||
__IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ |
|||
|
|||
__IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< SMBUS Error code */ |
|||
|
|||
__IO uint32_t Devaddress; /*!< SMBUS Target device address */ |
|||
|
|||
__IO uint32_t EventCount; /*!< SMBUS Event counter */ |
|||
|
|||
uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */ |
|||
|
|||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
|||
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ |
|||
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ |
|||
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ |
|||
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ |
|||
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ |
|||
void (* MemTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Memory Tx Transfer completed callback */ |
|||
void (* MemRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Memory Rx Transfer completed callback */ |
|||
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ |
|||
void (* AbortCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Abort callback */ |
|||
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ |
|||
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
|||
} SMBUS_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL SMBUS Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ |
|||
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ |
|||
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ |
|||
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ |
|||
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ |
|||
HAL_SMBUS_ERROR_CB_ID = 0x07U, /*!< SMBUS Error callback ID */ |
|||
HAL_SMBUS_ABORT_CB_ID = 0x08U, /*!< SMBUS Abort callback ID */ |
|||
HAL_SMBUS_MSPINIT_CB_ID = 0x09U, /*!< SMBUS Msp Init callback ID */ |
|||
HAL_SMBUS_MSPDEINIT_CB_ID = 0x0AU /*!< SMBUS Msp DeInit callback ID */ |
|||
|
|||
} HAL_SMBUS_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SMBUS Callback pointer definition |
|||
*/ |
|||
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an I2C callback function */ |
|||
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ |
|||
|
|||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code
|
|||
* @brief SMBUS Error Code |
|||
* @{ |
|||
*/ |
|||
#define HAL_SMBUS_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_SMBUS_ERROR_BERR 0x00000001U /*!< BERR error */ |
|||
#define HAL_SMBUS_ERROR_ARLO 0x00000002U /*!< ARLO error */ |
|||
#define HAL_SMBUS_ERROR_AF 0x00000004U /*!< AF error */ |
|||
#define HAL_SMBUS_ERROR_OVR 0x00000008U /*!< OVR error */ |
|||
#define HAL_SMBUS_ERROR_TIMEOUT 0x00000010U /*!< Timeout Error */ |
|||
#define HAL_SMBUS_ERROR_ALERT 0x00000020U /*!< Alert error */ |
|||
#define HAL_SMBUS_ERROR_PECERR 0x00000040U /*!< PEC error */ |
|||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
|||
#define HAL_SMBUS_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_ANALOGFILTER_ENABLE 0x00000000U |
|||
#define SMBUS_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_ADDRESSINGMODE_7BIT 0x00004000U |
|||
#define SMBUS_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_DUALADDRESS_DISABLE 0x00000000U |
|||
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_GENERALCALL_DISABLE 0x00000000U |
|||
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_ENGC |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_NOSTRETCH_DISABLE 0x00000000U |
|||
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_PEC_DISABLE 0x00000000U |
|||
#define SMBUS_PEC_ENABLE I2C_CR1_ENPEC |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) |
|||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE I2C_CR1_SMBUS |
|||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_XferDirection_definition SMBUS XferDirection definition
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_DIRECTION_RECEIVE 0x00000000U |
|||
#define SMBUS_DIRECTION_TRANSMIT 0x00000001U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_FIRST_FRAME 0x00000001U |
|||
#define SMBUS_NEXT_FRAME 0x00000002U |
|||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC 0x00000003U |
|||
#define SMBUS_LAST_FRAME_NO_PEC 0x00000004U |
|||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC 0x00000005U |
|||
#define SMBUS_LAST_FRAME_WITH_PEC 0x00000006U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_IT_BUF I2C_CR2_ITBUFEN |
|||
#define SMBUS_IT_EVT I2C_CR2_ITEVTEN |
|||
#define SMBUS_IT_ERR I2C_CR2_ITERREN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_FLAG_SMBALERT 0x00018000U |
|||
#define SMBUS_FLAG_TIMEOUT 0x00014000U |
|||
#define SMBUS_FLAG_PECERR 0x00011000U |
|||
#define SMBUS_FLAG_OVR 0x00010800U |
|||
#define SMBUS_FLAG_AF 0x00010400U |
|||
#define SMBUS_FLAG_ARLO 0x00010200U |
|||
#define SMBUS_FLAG_BERR 0x00010100U |
|||
#define SMBUS_FLAG_TXE 0x00010080U |
|||
#define SMBUS_FLAG_RXNE 0x00010040U |
|||
#define SMBUS_FLAG_STOPF 0x00010010U |
|||
#define SMBUS_FLAG_ADD10 0x00010008U |
|||
#define SMBUS_FLAG_BTF 0x00010004U |
|||
#define SMBUS_FLAG_ADDR 0x00010002U |
|||
#define SMBUS_FLAG_SB 0x00010001U |
|||
#define SMBUS_FLAG_DUALF 0x00100080U |
|||
#define SMBUS_FLAG_SMBHOST 0x00100040U |
|||
#define SMBUS_FLAG_SMBDEFAULT 0x00100020U |
|||
#define SMBUS_FLAG_GENCALL 0x00100010U |
|||
#define SMBUS_FLAG_TRA 0x00100004U |
|||
#define SMBUS_FLAG_BUSY 0x00100002U |
|||
#define SMBUS_FLAG_MSL 0x00100001U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SMBUS handle state
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
|||
#endif |
|||
|
|||
/** @brief Enable or disable the specified SMBUS interrupts.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMBUS_IT_BUF: Buffer interrupt enable |
|||
* @arg SMBUS_IT_EVT: Event interrupt enable |
|||
* @arg SMBUS_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
|||
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) |
|||
|
|||
/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMBUS_IT_BUF: Buffer interrupt enable |
|||
* @arg SMBUS_IT_EVT: Event interrupt enable |
|||
* @arg SMBUS_IT_ERR: Error interrupt enable |
|||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks whether the specified SMBUS flag is set or not.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SMBUS_FLAG_SMBALERT: SMBus Alert flag |
|||
* @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow error flag |
|||
* @arg SMBUS_FLAG_PECERR: PEC error in reception flag |
|||
* @arg SMBUS_FLAG_OVR: Overrun/Underrun flag |
|||
* @arg SMBUS_FLAG_AF: Acknowledge failure flag |
|||
* @arg SMBUS_FLAG_ARLO: Arbitration lost flag |
|||
* @arg SMBUS_FLAG_BERR: Bus error flag |
|||
* @arg SMBUS_FLAG_TXE: Data register empty flag |
|||
* @arg SMBUS_FLAG_RXNE: Data register not empty flag |
|||
* @arg SMBUS_FLAG_STOPF: Stop detection flag |
|||
* @arg SMBUS_FLAG_ADD10: 10-bit header sent flag |
|||
* @arg SMBUS_FLAG_BTF: Byte transfer finished flag |
|||
* @arg SMBUS_FLAG_ADDR: Address sent flag |
|||
* Address matched flag |
|||
* @arg SMBUS_FLAG_SB: Start bit flag |
|||
* @arg SMBUS_FLAG_DUALF: Dual flag |
|||
* @arg SMBUS_FLAG_SMBHOST: SMBus host header |
|||
* @arg SMBUS_FLAG_SMBDEFAULT: SMBus default header |
|||
* @arg SMBUS_FLAG_GENCALL: General call header flag |
|||
* @arg SMBUS_FLAG_TRA: Transmitter/Receiver flag |
|||
* @arg SMBUS_FLAG_BUSY: Bus busy flag |
|||
* @arg SMBUS_FLAG_MSL: Master/Slave flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)): \ |
|||
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
|||
|
|||
/** @brief Clears the SMBUS pending flags which are cleared by writing 0 in a specific bit.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg SMBUS_FLAG_SMBALERT: SMBus Alert flag |
|||
* @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow error flag |
|||
* @arg SMBUS_FLAG_PECERR: PEC error in reception flag |
|||
* @arg SMBUS_FLAG_OVR: Overrun/Underrun flag (Slave mode) |
|||
* @arg SMBUS_FLAG_AF: Acknowledge failure flag |
|||
* @arg SMBUS_FLAG_ARLO: Arbitration lost flag (Master mode) |
|||
* @arg SMBUS_FLAG_BERR: Bus error flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & SMBUS_FLAG_MASK)) |
|||
|
|||
/** @brief Clears the SMBUS ADDR pending flag.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_CLEAR_ADDRFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR1; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR2; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0) |
|||
|
|||
/** @brief Clears the SMBUS STOPF pending flag.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_CLEAR_STOPFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR1; \ |
|||
(__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0) |
|||
|
|||
/** @brief Enable the SMBUS peripheral.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) |
|||
|
|||
/** @brief Disable the SMBUS peripheral.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) |
|||
|
|||
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
|
|||
* @param __HANDLE__ specifies the SMBUS Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_ACK)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SMBUS_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
|||
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
|||
|
|||
/* Callbacks Register/UnRegister functions ************************************/ |
|||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* IO operation functions *****************************************************/ |
|||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
|||
* @{ |
|||
*/ |
|||
/******* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
|||
* @{ |
|||
*/ |
|||
/******* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
|||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
|
|||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
|||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
|||
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
|||
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
|||
|
|||
/****** Filter Configuration functions */ |
|||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) |
|||
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); |
|||
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); |
|||
#endif |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|||
* @{ |
|||
*/ |
|||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
|||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Peripheral State, mode and Errors functions **************************************************/ |
|||
HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
|||
HAL_SMBUS_ModeTypeDef HAL_SMBUS_GetMode(SMBUS_HandleTypeDef *hsmbus); |
|||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup SMBUS_Private_Constants SMBUS Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define SMBUS_FLAG_MASK 0x0000FFFFU |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup SMBUS_Private_Macros SMBUS Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define SMBUS_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) |
|||
|
|||
#define SMBUS_RISE_TIME(__FREQRANGE__) ( ((__FREQRANGE__) + 1U)) |
|||
|
|||
#define SMBUS_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) |
|||
|
|||
#define SMBUS_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) |
|||
|
|||
#define SMBUS_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) |
|||
|
|||
#define SMBUS_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) |
|||
|
|||
#define SMBUS_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) |
|||
|
|||
#define SMBUS_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) |
|||
|
|||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ENPEC) |
|||
|
|||
#define SMBUS_GET_PEC_VALUE(__HANDLE__) ((__HANDLE__)->XferPEC) |
|||
|
|||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) |
|||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
|||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
|||
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
|||
#endif |
|||
#define IS_SMBUS_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
|||
((ADDRESS) == SMBUS_ADDRESSINGMODE_10BIT)) |
|||
|
|||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
|||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
|||
|
|||
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ |
|||
((CALL) == SMBUS_GENERALCALL_ENABLE)) |
|||
|
|||
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
|||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
|||
|
|||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
|||
((PEC) == SMBUS_PEC_ENABLE)) |
|||
|
|||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
|||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
|||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
|||
|
|||
#define IS_SMBUS_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 100000U)) |
|||
|
|||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) |
|||
|
|||
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) |
|||
|
|||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ |
|||
((REQUEST) == SMBUS_NEXT_FRAME) || \ |
|||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
|||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
|||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
|||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private Functions ---------------------------------------------------------*/ |
|||
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* __STM32F4xx_HAL_SMBUS_H */ |
|||
|
|||
@ -0,0 +1,604 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_spdifrx.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SPDIFRX HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_SPDIFRX_H |
|||
#define STM32F4xx_HAL_SPDIFRX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
#if defined(STM32F446xx) |
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (SPDIFRX) |
|||
|
|||
/** @addtogroup SPDIFRX
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief SPDIFRX Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
|
|||
This parameter can be a value of @ref SPDIFRX_Input_Selection */ |
|||
|
|||
uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
|
|||
This parameter can be a value of @ref SPDIFRX_Max_Retries */ |
|||
|
|||
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
|
|||
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ |
|||
|
|||
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
|
|||
This parameter can be a value of @ref SPDIFRX_Channel_Selection */ |
|||
|
|||
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
|
|||
This parameter can be a value of @ref SPDIFRX_Data_Format */ |
|||
|
|||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
|||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ |
|||
|
|||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_PT_Mask */ |
|||
|
|||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ |
|||
|
|||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_V_Mask */ |
|||
|
|||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_PE_Mask */ |
|||
} SPDIFRX_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief SPDIFRX SetDataFormat structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
|
|||
This parameter can be a value of @ref SPDIFRX_Data_Format */ |
|||
|
|||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
|||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ |
|||
|
|||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_PT_Mask */ |
|||
|
|||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ |
|||
|
|||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_V_Mask */ |
|||
|
|||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
|||
This parameter can be a value of @ref SPDIFRX_PE_Mask */ |
|||
|
|||
} SPDIFRX_SetDataFormatTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */ |
|||
HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */ |
|||
HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */ |
|||
HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */ |
|||
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */ |
|||
HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */ |
|||
} HAL_SPDIFRX_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief SPDIFRX handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) |
|||
typedef struct __SPDIFRX_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ |
|||
{ |
|||
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ |
|||
|
|||
SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */ |
|||
|
|||
uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */ |
|||
|
|||
uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */ |
|||
|
|||
__IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
|
|||
(This field is initialized at the |
|||
same value as transfer size at the |
|||
beginning of the transfer and |
|||
decremented when a sample is received. |
|||
NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
|||
|
|||
__IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */ |
|||
|
|||
__IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
|
|||
(This field is initialized at the |
|||
same value as transfer size at the |
|||
beginning of the transfer and |
|||
decremented when a sample is received. |
|||
NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
|||
|
|||
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ |
|||
|
|||
__IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */ |
|||
|
|||
__IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /* SPDIFRX Error code */ |
|||
|
|||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) |
|||
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */ |
|||
void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */ |
|||
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */ |
|||
void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ |
|||
void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ |
|||
void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */ |
|||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ |
|||
|
|||
} SPDIFRX_HandleTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL SPDIFRX Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, /*!< SPDIFRX Data flow half completed callback ID */ |
|||
HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, /*!< SPDIFRX Data flow completed callback */ |
|||
HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, /*!< SPDIFRX Control flow half completed callback */ |
|||
HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U, /*!< SPDIFRX Control flow completed callback */ |
|||
HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */ |
|||
HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */ |
|||
HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */ |
|||
} HAL_SPDIFRX_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SPDIFRX Callback pointer definition |
|||
*/ |
|||
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */ |
|||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
|
|||
* @{ |
|||
*/ |
|||
/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
|||
#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ |
|||
#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ |
|||
#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */ |
|||
#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ |
|||
#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */ |
|||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) |
|||
#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U) |
|||
#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U) |
|||
#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U) |
|||
#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U) |
|||
#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */ |
|||
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U) |
|||
#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U) |
|||
#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_State SPDIFRX State
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU) |
|||
#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U) |
|||
#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE) |
|||
#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE) |
|||
#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE) |
|||
#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE) |
|||
#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE) |
|||
#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE) |
|||
#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE ) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
|
|||
* @{ |
|||
*/ |
|||
#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE) |
|||
#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE) |
|||
#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR) |
|||
#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR) |
|||
#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD) |
|||
#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD) |
|||
#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR) |
|||
#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR) |
|||
#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SPDIFRX handle state
|
|||
* @param __HANDLE__ SPDIFRX handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\ |
|||
(__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ |
|||
(__HANDLE__)->MspInitCallback = NULL;\ |
|||
(__HANDLE__)->MspDeInitCallback = NULL;\ |
|||
}while(0) |
|||
#else |
|||
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET) |
|||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
|
|||
* @param __HANDLE__ specifies the SPDIFRX Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) |
|||
|
|||
/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
|
|||
* @param __HANDLE__ specifies the SPDIFRX Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) |
|||
|
|||
|
|||
/** @brief Enable the specified SPDIFRX peripheral (RCV State).
|
|||
* @param __HANDLE__ specifies the SPDIFRX Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) |
|||
|
|||
|
|||
/** @brief Enable or disable the specified SPDIFRX interrupts.
|
|||
* @param __HANDLE__ specifies the SPDIFRX Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPDIFRX_IT_RXNE |
|||
* @arg SPDIFRX_IT_CSRNE |
|||
* @arg SPDIFRX_IT_PERRIE |
|||
* @arg SPDIFRX_IT_OVRIE |
|||
* @arg SPDIFRX_IT_SBLKIE |
|||
* @arg SPDIFRX_IT_SYNCDIE |
|||
* @arg SPDIFRX_IT_IFEIE |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) |
|||
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\ |
|||
&= (uint16_t)(~(__INTERRUPT__))) |
|||
|
|||
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__ specifies the SPDIFRX Handle. |
|||
* @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPDIFRX_IT_RXNE |
|||
* @arg SPDIFRX_IT_CSRNE |
|||
* @arg SPDIFRX_IT_PERRIE |
|||
* @arg SPDIFRX_IT_OVRIE |
|||
* @arg SPDIFRX_IT_SBLKIE |
|||
* @arg SPDIFRX_IT_SYNCDIE |
|||
* @arg SPDIFRX_IT_IFEIE |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks whether the specified SPDIFRX flag is set or not.
|
|||
* @param __HANDLE__ specifies the SPDIFRX Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPDIFRX_FLAG_RXNE |
|||
* @arg SPDIFRX_FLAG_CSRNE |
|||
* @arg SPDIFRX_FLAG_PERR |
|||
* @arg SPDIFRX_FLAG_OVR |
|||
* @arg SPDIFRX_FLAG_SBD |
|||
* @arg SPDIFRX_FLAG_SYNCD |
|||
* @arg SPDIFRX_FLAG_FERR |
|||
* @arg SPDIFRX_FLAG_SERR |
|||
* @arg SPDIFRX_FLAG_TERR |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ |
|||
& (__FLAG__)) == (__FLAG__)) ? SET : RESET) |
|||
|
|||
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set |
|||
* to clear the corresponding interrupt |
|||
* This parameter can be one of the following values: |
|||
* @arg SPDIFRX_FLAG_PERR |
|||
* @arg SPDIFRX_FLAG_OVR |
|||
* @arg SPDIFRX_SR_SBD |
|||
* @arg SPDIFRX_SR_SYNCD |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SPDIFRX_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SPDIFRX_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif); |
|||
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); |
|||
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, |
|||
pSPDIFRX_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, |
|||
HAL_SPDIFRX_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SPDIFRX_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ***************************************************/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, |
|||
uint32_t Timeout); |
|||
|
|||
/* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
|||
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif); |
|||
|
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif); |
|||
|
|||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
|||
void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
|||
void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
|||
void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif); |
|||
void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
|||
void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SPDIFRX_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control and State functions ************************************/ |
|||
HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif); |
|||
uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ |
|||
((INPUT) == SPDIFRX_INPUT_IN2) || \ |
|||
((INPUT) == SPDIFRX_INPUT_IN3) || \ |
|||
((INPUT) == SPDIFRX_INPUT_IN0)) |
|||
|
|||
#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ |
|||
((RET) == SPDIFRX_MAXRETRIES_3) || \ |
|||
((RET) == SPDIFRX_MAXRETRIES_15) || \ |
|||
((RET) == SPDIFRX_MAXRETRIES_63)) |
|||
|
|||
#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ |
|||
((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) |
|||
|
|||
#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ |
|||
((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) |
|||
|
|||
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ |
|||
((VAL) == SPDIFRX_VALIDITYMASK_ON)) |
|||
|
|||
#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ |
|||
((VAL) == SPDIFRX_PARITYERRORMASK_ON)) |
|||
|
|||
#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ |
|||
((CHANNEL) == SPDIFRX_CHANNEL_B)) |
|||
|
|||
#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ |
|||
((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ |
|||
((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) |
|||
|
|||
#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ |
|||
((MODE) == SPDIFRX_STEREOMODE_ENABLE)) |
|||
|
|||
#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ |
|||
((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* SPDIFRX */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* STM32F446xx */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32F4xx_HAL_SPDIFRX_H */ |
|||
@ -0,0 +1,729 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_spi.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SPI HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_SPI_H |
|||
#define STM32F4xx_HAL_SPI_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SPI
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief SPI Configuration Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
|||
This parameter can be a value of @ref SPI_Mode */ |
|||
|
|||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
|||
This parameter can be a value of @ref SPI_Direction */ |
|||
|
|||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
|||
This parameter can be a value of @ref SPI_Data_Size */ |
|||
|
|||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
|||
This parameter can be a value of @ref SPI_Clock_Polarity */ |
|||
|
|||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
|||
This parameter can be a value of @ref SPI_Clock_Phase */ |
|||
|
|||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
|||
hardware (NSS pin) or by software using the SSI bit. |
|||
This parameter can be a value of @ref SPI_Slave_Select_management */ |
|||
|
|||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
|||
used to configure the transmit and receive SCK clock. |
|||
This parameter can be a value of @ref SPI_BaudRate_Prescaler |
|||
@note The communication clock is derived from the master |
|||
clock. The slave clock does not need to be set. */ |
|||
|
|||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
|||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
|||
|
|||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
|||
This parameter can be a value of @ref SPI_TI_mode */ |
|||
|
|||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
|||
This parameter can be a value of @ref SPI_CRC_Calculation */ |
|||
|
|||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
|||
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ |
|||
} SPI_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SPI State structure definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
|||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
|||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
|||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
|||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
|||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
|||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
|||
} HAL_SPI_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief SPI handle Structure definition |
|||
*/ |
|||
typedef struct __SPI_HandleTypeDef |
|||
{ |
|||
SPI_TypeDef *Instance; /*!< SPI registers base address */ |
|||
|
|||
SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
|||
|
|||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
|||
|
|||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
|||
|
|||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
|||
|
|||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
|||
|
|||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
|||
|
|||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< SPI Error code */ |
|||
|
|||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|||
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ |
|||
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ |
|||
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ |
|||
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ |
|||
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ |
|||
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ |
|||
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ |
|||
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ |
|||
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|||
} SPI_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|||
/**
|
|||
* @brief HAL SPI Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ |
|||
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ |
|||
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ |
|||
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ |
|||
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ |
|||
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ |
|||
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ |
|||
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ |
|||
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ |
|||
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ |
|||
|
|||
} HAL_SPI_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SPI Callback pointer definition |
|||
*/ |
|||
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ |
|||
|
|||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Error_Code SPI Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ |
|||
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ |
|||
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ |
|||
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ |
|||
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ |
|||
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
|||
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ |
|||
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ |
|||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Mode SPI Mode
|
|||
* @{ |
|||
*/ |
|||
#define SPI_MODE_SLAVE (0x00000000U) |
|||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Direction SPI Direction Mode
|
|||
* @{ |
|||
*/ |
|||
#define SPI_DIRECTION_2LINES (0x00000000U) |
|||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
|||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Data_Size SPI Data Size
|
|||
* @{ |
|||
*/ |
|||
#define SPI_DATASIZE_8BIT (0x00000000U) |
|||
#define SPI_DATASIZE_16BIT SPI_CR1_DFF |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
|||
* @{ |
|||
*/ |
|||
#define SPI_POLARITY_LOW (0x00000000U) |
|||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
|||
* @{ |
|||
*/ |
|||
#define SPI_PHASE_1EDGE (0x00000000U) |
|||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
|||
* @{ |
|||
*/ |
|||
#define SPI_NSS_SOFT SPI_CR1_SSM |
|||
#define SPI_NSS_HARD_INPUT (0x00000000U) |
|||
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
|||
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) |
|||
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) |
|||
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) |
|||
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) |
|||
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) |
|||
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) |
|||
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
|||
* @{ |
|||
*/ |
|||
#define SPI_FIRSTBIT_MSB (0x00000000U) |
|||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_TI_mode SPI TI Mode
|
|||
* @{ |
|||
*/ |
|||
#define SPI_TIMODE_DISABLE (0x00000000U) |
|||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
|||
* @{ |
|||
*/ |
|||
#define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
|||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
|||
* @{ |
|||
*/ |
|||
#define SPI_IT_TXE SPI_CR2_TXEIE |
|||
#define SPI_IT_RXNE SPI_CR2_RXNEIE |
|||
#define SPI_IT_ERR SPI_CR2_ERRIE |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
|||
* @{ |
|||
*/ |
|||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
|||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
|||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
|||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
|||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
|||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
|||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
|||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ |
|||
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SPI handle state.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
|||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Enable the specified SPI interrupts.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg SPI_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
|||
|
|||
/** @brief Disable the specified SPI interrupts.
|
|||
* @param __HANDLE__ specifies the SPI handle. |
|||
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @param __INTERRUPT__ specifies the interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg SPI_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
|||
|
|||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @param __INTERRUPT__ specifies the SPI interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg SPI_IT_ERR: Error interrupt enable |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Check whether the specified SPI flag is set or not.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
|||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag |
|||
* @arg SPI_FLAG_CRCERR: CRC error flag |
|||
* @arg SPI_FLAG_MODF: Mode fault flag |
|||
* @arg SPI_FLAG_OVR: Overrun flag |
|||
* @arg SPI_FLAG_BSY: Busy flag |
|||
* @arg SPI_FLAG_FRE: Frame format error flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clear the SPI CRCERR pending flag.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
|||
|
|||
/** @brief Clear the SPI MODF pending flag.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg_modf = 0x00U; \ |
|||
tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
|||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
|||
UNUSED(tmpreg_modf); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Clear the SPI OVR pending flag.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg_ovr = 0x00U; \ |
|||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
|||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
|||
UNUSED(tmpreg_ovr); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Clear the SPI FRE pending flag.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg_fre = 0x00U; \ |
|||
tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
|||
UNUSED(tmpreg_fre); \ |
|||
}while(0U) |
|||
|
|||
/** @brief Enable the SPI peripheral.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
|||
|
|||
/** @brief Disable the SPI peripheral.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Set the SPI transmit-only mode.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
|||
|
|||
/** @brief Set the SPI receive-only mode.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
|||
|
|||
/** @brief Reset the CRC calculation of the SPI.
|
|||
* @param __HANDLE__ specifies the SPI Handle. |
|||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
|||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) |
|||
|
|||
/** @brief Check whether the specified SPI flag is set or not.
|
|||
* @param __SR__ copy of SPI SR register. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
|||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag |
|||
* @arg SPI_FLAG_CRCERR: CRC error flag |
|||
* @arg SPI_FLAG_MODF: Mode fault flag |
|||
* @arg SPI_FLAG_OVR: Overrun flag |
|||
* @arg SPI_FLAG_BSY: Busy flag |
|||
* @arg SPI_FLAG_FRE: Frame format error flag |
|||
* @retval SET or RESET. |
|||
*/ |
|||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ |
|||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) |
|||
|
|||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
|||
* @param __CR2__ copy of SPI CR2 register. |
|||
* @param __INTERRUPT__ specifies the SPI interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
|||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
|||
* @arg SPI_IT_ERR: Error interrupt enable |
|||
* @retval SET or RESET. |
|||
*/ |
|||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ |
|||
(__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
|||
* @param __MODE__ specifies the SPI Mode. |
|||
* This parameter can be a value of @ref SPI_Mode |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ |
|||
((__MODE__) == SPI_MODE_MASTER)) |
|||
|
|||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
|||
* @param __MODE__ specifies the SPI Direction Mode. |
|||
* This parameter can be a value of @ref SPI_Direction |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
|||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
|||
((__MODE__) == SPI_DIRECTION_1LINE)) |
|||
|
|||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
|||
* @param __MODE__ specifies the SPI Direction Mode. |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
|||
|
|||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
|||
* @param __MODE__ specifies the SPI Direction Mode. |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
|||
((__MODE__) == SPI_DIRECTION_1LINE)) |
|||
|
|||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
|||
* @param __DATASIZE__ specifies the SPI Data Size. |
|||
* This parameter can be a value of @ref SPI_Data_Size |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
|||
((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
|||
|
|||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
|||
* @param __CPOL__ specifies the SPI serial clock steady state. |
|||
* This parameter can be a value of @ref SPI_Clock_Polarity |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
|||
((__CPOL__) == SPI_POLARITY_HIGH)) |
|||
|
|||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
|||
* @param __CPHA__ specifies the SPI Clock Phase. |
|||
* This parameter can be a value of @ref SPI_Clock_Phase |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
|||
((__CPHA__) == SPI_PHASE_2EDGE)) |
|||
|
|||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
|||
* @param __NSS__ specifies the SPI Slave Select management parameter. |
|||
* This parameter can be a value of @ref SPI_Slave_Select_management |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
|||
((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
|||
((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
|||
|
|||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
|||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler. |
|||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
|||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
|||
|
|||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
|||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
|||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
|||
((__BIT__) == SPI_FIRSTBIT_LSB)) |
|||
|
|||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
|||
* @param __MODE__ specifies the SPI TI mode. |
|||
* This parameter can be a value of @ref SPI_TI_mode |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
|||
((__MODE__) == SPI_TIMODE_ENABLE)) |
|||
|
|||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
|||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state. |
|||
* This parameter can be a value of @ref SPI_CRC_Calculation |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
|||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
|||
|
|||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
|||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. |
|||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ |
|||
((__POLYNOMIAL__) <= 0xFFFFU) && \ |
|||
(((__POLYNOMIAL__)&0x1U) != 0U)) |
|||
|
|||
/** @brief Checks if DMA handle is valid.
|
|||
* @param __HANDLE__ specifies a DMA Handle. |
|||
* @retval None |
|||
*/ |
|||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SPI_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SPI_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
|||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
|||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, |
|||
pSPI_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SPI_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ***************************************************/ |
|||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
|||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
|||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
|||
/* Transfer Abort functions */ |
|||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
|||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
|||
|
|||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
|||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SPI_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State and Error functions ***************************************/ |
|||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
|||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_SPI_H */ |
|||
|
|||
@ -0,0 +1,236 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_sram.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SRAM HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_SRAM_H |
|||
#define STM32F4xx_HAL_SRAM_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(FMC_Bank1) || defined(FSMC_Bank1) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#if defined(FSMC_Bank1) |
|||
#include "stm32f4xx_ll_fsmc.h" |
|||
#else |
|||
#include "stm32f4xx_ll_fmc.h" |
|||
#endif /* FSMC_Bank1 */ |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
/** @addtogroup SRAM
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported typedef ----------------------------------------------------------*/ |
|||
|
|||
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
|||
* @{ |
|||
*/ |
|||
/**
|
|||
* @brief HAL SRAM State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ |
|||
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ |
|||
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ |
|||
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ |
|||
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ |
|||
|
|||
} HAL_SRAM_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief SRAM handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|||
typedef struct __SRAM_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|||
{ |
|||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
|||
|
|||
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
|||
|
|||
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
|||
|
|||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
|||
|
|||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|||
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ |
|||
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ |
|||
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ |
|||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|||
} SRAM_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL SRAM Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ |
|||
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ |
|||
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ |
|||
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ |
|||
} HAL_SRAM_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL SRAM Callback pointer definition |
|||
*/ |
|||
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); |
|||
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); |
|||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset SRAM handle state
|
|||
* @param __HANDLE__ SRAM handle |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
|||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions ********************************/ |
|||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, |
|||
FMC_NORSRAM_TimingTypeDef *ExtTiming); |
|||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
|||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
|||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* I/O operation functions ***************************************************/ |
|||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
|||
uint32_t BufferSize); |
|||
|
|||
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
|||
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
|||
|
|||
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
|||
/* SRAM callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, |
|||
pSRAM_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); |
|||
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, |
|||
pSRAM_DmaCallbackTypeDef pCallback); |
|||
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* SRAM Control functions ****************************************************/ |
|||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
|||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* SRAM State functions ******************************************************/ |
|||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* FMC_Bank1 || FSMC_Bank1 */ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_SRAM_H */ |
|||
@ -0,0 +1,909 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_uart.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of UART HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_UART_H |
|||
#define __STM32F4xx_HAL_UART_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup UART
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup UART_Exported_Types UART Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief UART Init Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
|||
The baud rate is computed using the following formula: |
|||
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) |
|||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 |
|||
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ |
|||
|
|||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
|||
This parameter can be a value of @ref UART_Word_Length */ |
|||
|
|||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
|||
This parameter can be a value of @ref UART_Stop_Bits */ |
|||
|
|||
uint32_t Parity; /*!< Specifies the parity mode.
|
|||
This parameter can be a value of @ref UART_Parity |
|||
@note When parity is enabled, the computed parity is inserted |
|||
at the MSB position of the transmitted data (9th bit when |
|||
the word length is set to 9 data bits; 8th bit when the |
|||
word length is set to 8 data bits). */ |
|||
|
|||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
|||
This parameter can be a value of @ref UART_Mode */ |
|||
|
|||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
|
|||
This parameter can be a value of @ref UART_Hardware_Flow_Control */ |
|||
|
|||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
|
|||
This parameter can be a value of @ref UART_Over_Sampling */ |
|||
} UART_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL UART State structures definition |
|||
* @note HAL UART State value is a combination of 2 different substates: gState and RxState. |
|||
* - gState contains UART state information related to global Handle management |
|||
* and also information related to Tx operations. |
|||
* gState value coding follow below described bitmap : |
|||
* b7-b6 Error information |
|||
* 00 : No Error |
|||
* 01 : (Not Used) |
|||
* 10 : Timeout |
|||
* 11 : Error |
|||
* b5 Peripheral initialization status |
|||
* 0 : Reset (Peripheral not initialized) |
|||
* 1 : Init done (Peripheral initialized. HAL UART Init function already called) |
|||
* b4-b3 (not used) |
|||
* xx : Should be set to 00 |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (Peripheral busy with some configuration or internal operations) |
|||
* b1 (not used) |
|||
* x : Should be set to 0 |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* - RxState contains information related to Rx operations. |
|||
* RxState value coding follow below described bitmap : |
|||
* b7-b6 (not used) |
|||
* xx : Should be set to 00 |
|||
* b5 Peripheral initialization status |
|||
* 0 : Reset (Peripheral not initialized) |
|||
* 1 : Init done (Peripheral initialized) |
|||
* b4-b2 (not used) |
|||
* xxx : Should be set to 000 |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 (not used) |
|||
* x : Should be set to 0. |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
|||
Value is allowed for gState and RxState */ |
|||
HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
|||
Value is allowed for gState and RxState */ |
|||
HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
|||
Value is allowed for gState only */ |
|||
HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
|||
Value is allowed for gState only */ |
|||
HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
|||
Value is allowed for RxState only */ |
|||
HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
|||
Not to be used for neither gState nor RxState. |
|||
Value is result of combination (Or) between gState and RxState values */ |
|||
HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
|||
Value is allowed for gState only */ |
|||
HAL_UART_STATE_ERROR = 0xE0U /*!< Error
|
|||
Value is allowed for gState only */ |
|||
} HAL_UART_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL UART Reception type definition |
|||
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing. |
|||
* This parameter can be a value of @ref UART_Reception_Type_Values : |
|||
* HAL_UART_RECEPTION_STANDARD = 0x00U, |
|||
* HAL_UART_RECEPTION_TOIDLE = 0x01U, |
|||
*/ |
|||
typedef uint32_t HAL_UART_RxTypeTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL UART Rx Event type definition |
|||
* @note HAL UART Rx Event type value aims to identify which type of Event has occurred |
|||
* leading to call of the RxEvent callback. |
|||
* This parameter can be a value of @ref UART_RxEvent_Type_Values : |
|||
* HAL_UART_RXEVENT_TC = 0x00U, |
|||
* HAL_UART_RXEVENT_HT = 0x01U, |
|||
* HAL_UART_RXEVENT_IDLE = 0x02U, |
|||
*/ |
|||
typedef uint32_t HAL_UART_RxEventTypeTypeDef; |
|||
|
|||
/**
|
|||
* @brief UART handle Structure definition |
|||
*/ |
|||
typedef struct __UART_HandleTypeDef |
|||
{ |
|||
USART_TypeDef *Instance; /*!< UART registers base address */ |
|||
|
|||
UART_InitTypeDef Init; /*!< UART communication parameters */ |
|||
|
|||
const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ |
|||
|
|||
uint16_t TxXferSize; /*!< UART Tx Transfer size */ |
|||
|
|||
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ |
|||
|
|||
uint16_t RxXferSize; /*!< UART Rx Transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ |
|||
|
|||
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ |
|||
|
|||
__IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
|
|||
and also related to Tx operations. |
|||
This parameter can be a value of @ref HAL_UART_StateTypeDef */ |
|||
|
|||
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
|
|||
This parameter can be a value of @ref HAL_UART_StateTypeDef */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< UART Error code */ |
|||
|
|||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
|||
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ |
|||
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ |
|||
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ |
|||
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ |
|||
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ |
|||
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ |
|||
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ |
|||
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ |
|||
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ |
|||
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ |
|||
|
|||
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ |
|||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
|||
|
|||
} UART_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL UART Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ |
|||
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ |
|||
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ |
|||
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ |
|||
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ |
|||
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ |
|||
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ |
|||
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ |
|||
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ |
|||
|
|||
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ |
|||
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ |
|||
|
|||
} HAL_UART_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL UART Callback pointer definition |
|||
*/ |
|||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ |
|||
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ |
|||
|
|||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup UART_Exported_Constants UART Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup UART_Error_Code UART Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ |
|||
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ |
|||
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ |
|||
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ |
|||
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
|||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
|||
#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Word_Length UART Word Length
|
|||
* @{ |
|||
*/ |
|||
#define UART_WORDLENGTH_8B 0x00000000U |
|||
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
|
|||
* @{ |
|||
*/ |
|||
#define UART_STOPBITS_1 0x00000000U |
|||
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Parity UART Parity
|
|||
* @{ |
|||
*/ |
|||
#define UART_PARITY_NONE 0x00000000U |
|||
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) |
|||
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
|
|||
* @{ |
|||
*/ |
|||
#define UART_HWCONTROL_NONE 0x00000000U |
|||
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) |
|||
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) |
|||
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Mode UART Transfer Mode
|
|||
* @{ |
|||
*/ |
|||
#define UART_MODE_RX ((uint32_t)USART_CR1_RE) |
|||
#define UART_MODE_TX ((uint32_t)USART_CR1_TE) |
|||
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_State UART State
|
|||
* @{ |
|||
*/ |
|||
#define UART_STATE_DISABLE 0x00000000U |
|||
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Over_Sampling UART Over Sampling
|
|||
* @{ |
|||
*/ |
|||
#define UART_OVERSAMPLING_16 0x00000000U |
|||
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
|
|||
* @{ |
|||
*/ |
|||
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U |
|||
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
|
|||
* @{ |
|||
*/ |
|||
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U |
|||
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Flags UART FLags
|
|||
* Elements values convention: 0xXXXX |
|||
* - 0xXXXX : Flag mask in the SR register |
|||
* @{ |
|||
*/ |
|||
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) |
|||
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) |
|||
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) |
|||
#define UART_FLAG_TC ((uint32_t)USART_SR_TC) |
|||
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) |
|||
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) |
|||
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) |
|||
#define UART_FLAG_NE ((uint32_t)USART_SR_NE) |
|||
#define UART_FLAG_FE ((uint32_t)USART_SR_FE) |
|||
#define UART_FLAG_PE ((uint32_t)USART_SR_PE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
|
|||
* Elements values convention: 0xY000XXXX |
|||
* - XXXX : Interrupt mask (16 bits) in the Y register |
|||
* - Y : Interrupt source register (2bits) |
|||
* - 0001: CR1 register |
|||
* - 0010: CR2 register |
|||
* - 0011: CR3 register |
|||
* @{ |
|||
*/ |
|||
|
|||
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) |
|||
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) |
|||
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) |
|||
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) |
|||
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) |
|||
|
|||
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) |
|||
|
|||
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) |
|||
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_Reception_Type_Values UART Reception type values
|
|||
* @{ |
|||
*/ |
|||
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ |
|||
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
|
|||
* @{ |
|||
*/ |
|||
#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ |
|||
#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ |
|||
#define HAL_UART_RXEVENT_IDLE (0x00000002U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup UART_Exported_Macros UART Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset UART handle gstate & RxState
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0U) |
|||
#else |
|||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \ |
|||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ |
|||
} while(0U) |
|||
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Flushes the UART DR register
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
*/ |
|||
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) |
|||
|
|||
/** @brief Checks whether the specified UART flag is set or not.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) |
|||
* @arg UART_FLAG_LBD: LIN Break detection flag |
|||
* @arg UART_FLAG_TXE: Transmit data register empty flag |
|||
* @arg UART_FLAG_TC: Transmission Complete flag |
|||
* @arg UART_FLAG_RXNE: Receive data register not empty flag |
|||
* @arg UART_FLAG_IDLE: Idle Line detection flag |
|||
* @arg UART_FLAG_ORE: Overrun Error flag |
|||
* @arg UART_FLAG_NE: Noise Error flag |
|||
* @arg UART_FLAG_FE: Framing Error flag |
|||
* @arg UART_FLAG_PE: Parity Error flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clears the specified UART pending flag.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). |
|||
* @arg UART_FLAG_LBD: LIN Break detection flag. |
|||
* @arg UART_FLAG_TC: Transmission Complete flag. |
|||
* @arg UART_FLAG_RXNE: Receive data register not empty flag. |
|||
* |
|||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun |
|||
* error) and IDLE (Idle line detected) flags are cleared by software |
|||
* sequence: a read operation to USART_SR register followed by a read |
|||
* operation to USART_DR register. |
|||
* @note RXNE flag can be also cleared by a read to the USART_DR register. |
|||
* @note TC flag can be also cleared by software sequence: a read operation to |
|||
* USART_SR register followed by a write operation to USART_DR register. |
|||
* @note TXE flag is cleared only by a write to the USART_DR register. |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
|||
|
|||
/** @brief Clears the UART PE pending flag.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR; \ |
|||
tmpreg = (__HANDLE__)->Instance->DR; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Clears the UART FE pending flag.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clears the UART NE pending flag.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clears the UART ORE pending flag.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clears the UART IDLE pending flag.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Enable the specified UART interrupt.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __INTERRUPT__ specifies the UART interrupt source to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg UART_IT_CTS: CTS change interrupt |
|||
* @arg UART_IT_LBD: LIN Break detection interrupt |
|||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg UART_IT_TC: Transmission complete interrupt |
|||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg UART_IT_IDLE: Idle line detection interrupt |
|||
* @arg UART_IT_PE: Parity Error interrupt |
|||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ |
|||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) |
|||
|
|||
/** @brief Disable the specified UART interrupt.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __INTERRUPT__ specifies the UART interrupt source to disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg UART_IT_CTS: CTS change interrupt |
|||
* @arg UART_IT_LBD: LIN Break detection interrupt |
|||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg UART_IT_TC: Transmission complete interrupt |
|||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg UART_IT_IDLE: Idle line detection interrupt |
|||
* @arg UART_IT_PE: Parity Error interrupt |
|||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ |
|||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) |
|||
|
|||
/** @brief Checks whether the specified UART interrupt source is enabled or not.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* UART Handle selects the USARTx or UARTy peripheral |
|||
* (USART,UART availability and x,y values depending on device). |
|||
* @param __IT__ specifies the UART interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) |
|||
* @arg UART_IT_LBD: LIN Break detection interrupt |
|||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg UART_IT_TC: Transmission complete interrupt |
|||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg UART_IT_IDLE: Idle line detection interrupt |
|||
* @arg UART_IT_ERR: Error interrupt |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ |
|||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) |
|||
|
|||
/** @brief Enable CTS flow control
|
|||
* @note This macro allows to enable CTS hardware flow control for a given UART instance, |
|||
* without need to call HAL_UART_Init() function. |
|||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
|||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need |
|||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
|||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
|||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
|||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
|||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ |
|||
do{ \ |
|||
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ |
|||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ |
|||
} while(0U) |
|||
|
|||
/** @brief Disable CTS flow control
|
|||
* @note This macro allows to disable CTS hardware flow control for a given UART instance, |
|||
* without need to call HAL_UART_Init() function. |
|||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
|||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need |
|||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
|||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
|||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
|||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
|||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ |
|||
do{ \ |
|||
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ |
|||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Enable RTS flow control
|
|||
* This macro allows to enable RTS hardware flow control for a given UART instance, |
|||
* without need to call HAL_UART_Init() function. |
|||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
|||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need |
|||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
|||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
|||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
|||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
|||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ |
|||
do{ \ |
|||
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ |
|||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ |
|||
} while(0U) |
|||
|
|||
/** @brief Disable RTS flow control
|
|||
* This macro allows to disable RTS hardware flow control for a given UART instance, |
|||
* without need to call HAL_UART_Init() function. |
|||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
|||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need |
|||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
|||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
|||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
|||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
|||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ |
|||
do{ \ |
|||
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ |
|||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Macro to enable the UART's one bit sample method
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) |
|||
|
|||
/** @brief Macro to disable the UART's one bit sample method
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ |
|||
&= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) |
|||
|
|||
/** @brief Enable UART
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
|||
|
|||
/** @brief Disable UART
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup UART_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); |
|||
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); |
|||
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); |
|||
void HAL_UART_MspInit(UART_HandleTypeDef *huart); |
|||
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, |
|||
pUART_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); |
|||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* IO operation functions *******************************************************/ |
|||
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); |
|||
|
|||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); |
|||
|
|||
/* Transfer Abort functions */ |
|||
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); |
|||
|
|||
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); |
|||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); |
|||
|
|||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup UART_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ************************************************/ |
|||
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup UART_Exported_Functions_Group4
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions **************************************************/ |
|||
HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); |
|||
uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup UART_Private_Constants UART Private Constants
|
|||
* @{ |
|||
*/ |
|||
/** @brief UART interruptions flag mask
|
|||
* |
|||
*/ |
|||
#define UART_IT_MASK 0x0000FFFFU |
|||
|
|||
#define UART_CR1_REG_INDEX 1U |
|||
#define UART_CR2_REG_INDEX 2U |
|||
#define UART_CR3_REG_INDEX 3U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup UART_Private_Macros UART Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ |
|||
((LENGTH) == UART_WORDLENGTH_9B)) |
|||
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) |
|||
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ |
|||
((STOPBITS) == UART_STOPBITS_2)) |
|||
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ |
|||
((PARITY) == UART_PARITY_EVEN) || \ |
|||
((PARITY) == UART_PARITY_ODD)) |
|||
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ |
|||
(((CONTROL) == UART_HWCONTROL_NONE) || \ |
|||
((CONTROL) == UART_HWCONTROL_RTS) || \ |
|||
((CONTROL) == UART_HWCONTROL_CTS) || \ |
|||
((CONTROL) == UART_HWCONTROL_RTS_CTS)) |
|||
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) |
|||
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ |
|||
((STATE) == UART_STATE_ENABLE)) |
|||
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ |
|||
((SAMPLING) == UART_OVERSAMPLING_8)) |
|||
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) |
|||
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ |
|||
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) |
|||
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ |
|||
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) |
|||
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U) |
|||
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) |
|||
|
|||
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) |
|||
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) |
|||
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\ |
|||
+ 50U) / 100U) |
|||
/* UART BRR = mantissa + overflow + fraction
|
|||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ |
|||
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ |
|||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \ |
|||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) |
|||
|
|||
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) |
|||
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) |
|||
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\ |
|||
+ 50U) / 100U) |
|||
/* UART BRR = mantissa + overflow + fraction
|
|||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ |
|||
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ |
|||
((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \ |
|||
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup UART_Private_Functions UART Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_UART_H */ |
|||
|
|||
@ -0,0 +1,648 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_usart.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of USART HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_USART_H |
|||
#define __STM32F4xx_HAL_USART_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup USART
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup USART_Exported_Types USART Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief USART Init Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
|||
The baud rate is computed using the following formula: |
|||
- IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate))) |
|||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ |
|||
|
|||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
|||
This parameter can be a value of @ref USART_Word_Length */ |
|||
|
|||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
|||
This parameter can be a value of @ref USART_Stop_Bits */ |
|||
|
|||
uint32_t Parity; /*!< Specifies the parity mode.
|
|||
This parameter can be a value of @ref USART_Parity |
|||
@note When parity is enabled, the computed parity is inserted |
|||
at the MSB position of the transmitted data (9th bit when |
|||
the word length is set to 9 data bits; 8th bit when the |
|||
word length is set to 8 data bits). */ |
|||
|
|||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
|||
This parameter can be a value of @ref USART_Mode */ |
|||
|
|||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
|||
This parameter can be a value of @ref USART_Clock_Polarity */ |
|||
|
|||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
|||
This parameter can be a value of @ref USART_Clock_Phase */ |
|||
|
|||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
|||
data bit (MSB) has to be output on the SCLK pin in synchronous mode. |
|||
This parameter can be a value of @ref USART_Last_Bit */ |
|||
} USART_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ |
|||
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
|||
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ |
|||
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
|||
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ |
|||
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
|||
HAL_USART_STATE_ERROR = 0x04U /*!< Error */ |
|||
} HAL_USART_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief USART handle Structure definition |
|||
*/ |
|||
typedef struct __USART_HandleTypeDef |
|||
{ |
|||
USART_TypeDef *Instance; /*!< USART registers base address */ |
|||
|
|||
USART_InitTypeDef Init; /*!< Usart communication parameters */ |
|||
|
|||
const uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ |
|||
|
|||
uint16_t TxXferSize; /*!< Usart Tx Transfer size */ |
|||
|
|||
__IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */ |
|||
|
|||
uint16_t RxXferSize; /*!< Usart Rx Transfer size */ |
|||
|
|||
__IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< Locking object */ |
|||
|
|||
__IO HAL_USART_StateTypeDef State; /*!< Usart communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< USART Error code */ |
|||
|
|||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) |
|||
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ |
|||
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ |
|||
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ |
|||
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ |
|||
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ |
|||
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ |
|||
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ |
|||
|
|||
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ |
|||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ |
|||
|
|||
} USART_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL USART Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ |
|||
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ |
|||
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ |
|||
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ |
|||
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ |
|||
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ |
|||
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ |
|||
|
|||
HAL_USART_MSPINIT_CB_ID = 0x07U, /*!< USART MspInit callback ID */ |
|||
HAL_USART_MSPDEINIT_CB_ID = 0x08U /*!< USART MspDeInit callback ID */ |
|||
|
|||
} HAL_USART_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL USART Callback pointer definition |
|||
*/ |
|||
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ |
|||
|
|||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup USART_Exported_Constants USART Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup USART_Error_Code USART Error Code
|
|||
* @brief USART Error Code |
|||
* @{ |
|||
*/ |
|||
#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */ |
|||
#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */ |
|||
#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */ |
|||
#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */ |
|||
#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
|||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) |
|||
#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Word_Length USART Word Length
|
|||
* @{ |
|||
*/ |
|||
#define USART_WORDLENGTH_8B 0x00000000U |
|||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
|
|||
* @{ |
|||
*/ |
|||
#define USART_STOPBITS_1 0x00000000U |
|||
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) |
|||
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) |
|||
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Parity USART Parity
|
|||
* @{ |
|||
*/ |
|||
#define USART_PARITY_NONE 0x00000000U |
|||
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) |
|||
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Mode USART Mode
|
|||
* @{ |
|||
*/ |
|||
#define USART_MODE_RX ((uint32_t)USART_CR1_RE) |
|||
#define USART_MODE_TX ((uint32_t)USART_CR1_TE) |
|||
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Clock USART Clock
|
|||
* @{ |
|||
*/ |
|||
#define USART_CLOCK_DISABLE 0x00000000U |
|||
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Clock_Polarity USART Clock Polarity
|
|||
* @{ |
|||
*/ |
|||
#define USART_POLARITY_LOW 0x00000000U |
|||
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Clock_Phase USART Clock Phase
|
|||
* @{ |
|||
*/ |
|||
#define USART_PHASE_1EDGE 0x00000000U |
|||
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Last_Bit USART Last Bit
|
|||
* @{ |
|||
*/ |
|||
#define USART_LASTBIT_DISABLE 0x00000000U |
|||
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_NACK_State USART NACK State
|
|||
* @{ |
|||
*/ |
|||
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK) |
|||
#define USART_NACK_DISABLE 0x00000000U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Flags USART Flags
|
|||
* Elements values convention: 0xXXXX |
|||
* - 0xXXXX : Flag mask in the SR register |
|||
* @{ |
|||
*/ |
|||
#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE) |
|||
#define USART_FLAG_TC ((uint32_t)USART_SR_TC) |
|||
#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) |
|||
#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) |
|||
#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE) |
|||
#define USART_FLAG_NE ((uint32_t)USART_SR_NE) |
|||
#define USART_FLAG_FE ((uint32_t)USART_SR_FE) |
|||
#define USART_FLAG_PE ((uint32_t)USART_SR_PE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
|
|||
* Elements values convention: 0xY000XXXX |
|||
* - XXXX : Interrupt mask in the XX register |
|||
* - Y : Interrupt source register (2bits) |
|||
* - 01: CR1 register |
|||
* - 10: CR2 register |
|||
* - 11: CR3 register |
|||
* @{ |
|||
*/ |
|||
#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) |
|||
#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) |
|||
#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) |
|||
#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) |
|||
#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) |
|||
#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup USART_Exported_Macros USART Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset USART handle state
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_USART_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0U) |
|||
#else |
|||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) |
|||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ |
|||
|
|||
/** @brief Check whether the specified USART flag is set or not.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg USART_FLAG_TXE: Transmit data register empty flag |
|||
* @arg USART_FLAG_TC: Transmission Complete flag |
|||
* @arg USART_FLAG_RXNE: Receive data register not empty flag |
|||
* @arg USART_FLAG_IDLE: Idle Line detection flag |
|||
* @arg USART_FLAG_ORE: Overrun Error flag |
|||
* @arg USART_FLAG_NE: Noise Error flag |
|||
* @arg USART_FLAG_FE: Framing Error flag |
|||
* @arg USART_FLAG_PE: Parity Error flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** @brief Clear the specified USART pending flags.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg USART_FLAG_TC: Transmission Complete flag. |
|||
* @arg USART_FLAG_RXNE: Receive data register not empty flag. |
|||
* |
|||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun |
|||
* error) and IDLE (Idle line detected) flags are cleared by software |
|||
* sequence: a read operation to USART_SR register followed by a read |
|||
* operation to USART_DR register. |
|||
* @note RXNE flag can be also cleared by a read to the USART_DR register. |
|||
* @note TC flag can be also cleared by software sequence: a read operation to |
|||
* USART_SR register followed by a write operation to USART_DR register. |
|||
* @note TXE flag is cleared only by a write to the USART_DR register. |
|||
* |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
|||
|
|||
/** @brief Clear the USART PE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR; \ |
|||
tmpreg = (__HANDLE__)->Instance->DR; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0U) |
|||
|
|||
/** @brief Clear the USART FE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the USART NE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the USART ORE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Clear the USART IDLE pending flag.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) |
|||
|
|||
/** @brief Enables or disables the specified USART interrupts.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __INTERRUPT__ specifies the USART interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg USART_IT_TC: Transmission complete interrupt |
|||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg USART_IT_IDLE: Idle line detection interrupt |
|||
* @arg USART_IT_PE: Parity Error interrupt |
|||
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ |
|||
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) |
|||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ |
|||
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ |
|||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) |
|||
|
|||
/** @brief Checks whether the specified USART interrupt has occurred or not.
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @param __IT__ specifies the USART interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt |
|||
* @arg USART_IT_TC: Transmission complete interrupt |
|||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt |
|||
* @arg USART_IT_IDLE: Idle line detection interrupt |
|||
* @arg USART_IT_ERR: Error interrupt |
|||
* @arg USART_IT_PE: Parity Error interrupt |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \ |
|||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) |
|||
|
|||
/** @brief Macro to enable the USART's one bit sample method
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT) |
|||
|
|||
/** @brief Macro to disable the USART's one bit sample method
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ |
|||
&= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) |
|||
|
|||
/** @brief Enable USART
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
|||
|
|||
/** @brief Disable USART
|
|||
* @param __HANDLE__ specifies the USART Handle. |
|||
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device). |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup USART_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup USART_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); |
|||
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); |
|||
void HAL_USART_MspInit(USART_HandleTypeDef *husart); |
|||
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, |
|||
pUSART_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup USART_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* IO operation functions *******************************************************/ |
|||
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, |
|||
uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, |
|||
uint16_t Size); |
|||
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); |
|||
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); |
|||
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); |
|||
/* Transfer Abort functions */ |
|||
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); |
|||
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); |
|||
|
|||
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); |
|||
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); |
|||
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); |
|||
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); |
|||
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); |
|||
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); |
|||
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); |
|||
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup USART_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ************************************************/ |
|||
HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); |
|||
uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup USART_Private_Constants USART Private Constants
|
|||
* @{ |
|||
*/ |
|||
/** @brief USART interruptions flag mask
|
|||
* |
|||
*/ |
|||
#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ |
|||
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) |
|||
|
|||
#define USART_CR1_REG_INDEX 1U |
|||
#define USART_CR2_REG_INDEX 2U |
|||
#define USART_CR3_REG_INDEX 3U |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup USART_Private_Macros USART Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \ |
|||
((NACK) == USART_NACK_DISABLE)) |
|||
|
|||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ |
|||
((LASTBIT) == USART_LASTBIT_ENABLE)) |
|||
|
|||
#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || \ |
|||
((CPHA) == USART_PHASE_2EDGE)) |
|||
|
|||
#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || \ |
|||
((CPOL) == USART_POLARITY_HIGH)) |
|||
|
|||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \ |
|||
((CLOCK) == USART_CLOCK_ENABLE)) |
|||
|
|||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ |
|||
((LENGTH) == USART_WORDLENGTH_9B)) |
|||
|
|||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ |
|||
((STOPBITS) == USART_STOPBITS_0_5) || \ |
|||
((STOPBITS) == USART_STOPBITS_1_5) || \ |
|||
((STOPBITS) == USART_STOPBITS_2)) |
|||
|
|||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ |
|||
((PARITY) == USART_PARITY_EVEN) || \ |
|||
((PARITY) == USART_PARITY_ODD)) |
|||
|
|||
#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U)) |
|||
|
|||
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 12500000U) |
|||
|
|||
#define USART_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) |
|||
|
|||
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U) |
|||
|
|||
#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) |
|||
|
|||
/* UART BRR = mantissa + overflow + fraction
|
|||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ |
|||
|
|||
#define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \ |
|||
((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ |
|||
(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup USART_Private_Functions USART Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_USART_H */ |
|||
|
|||
@ -0,0 +1,298 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_wwdg.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of WWDG HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_HAL_WWDG_H |
|||
#define STM32F4xx_HAL_WWDG_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup WWDG
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup WWDG_Exported_Types WWDG Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief WWDG Init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
|
|||
This parameter can be a value of @ref WWDG_Prescaler */ |
|||
|
|||
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
|
|||
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ |
|||
|
|||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
|||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ |
|||
|
|||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
|
|||
This parameter can be a value of @ref WWDG_EWI_Mode */ |
|||
|
|||
} WWDG_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief WWDG handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) |
|||
typedef struct __WWDG_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ |
|||
{ |
|||
WWDG_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */ |
|||
|
|||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) |
|||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ |
|||
|
|||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ |
|||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ |
|||
} WWDG_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) |
|||
/**
|
|||
* @brief HAL WWDG common Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ |
|||
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ |
|||
} HAL_WWDG_CallbackIDTypeDef; |
|||
|
|||
/**
|
|||
* @brief HAL WWDG Callback pointer definition |
|||
*/ |
|||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ |
|||
|
|||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
|
|||
* @{ |
|||
*/ |
|||
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup WWDG_Flag_definition WWDG Flag definition
|
|||
* @brief WWDG Flag definition |
|||
* @{ |
|||
*/ |
|||
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup WWDG_Prescaler WWDG Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ |
|||
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ |
|||
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ |
|||
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
|
|||
* @{ |
|||
*/ |
|||
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ |
|||
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup WWDG_Private_Macros WWDG Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ |
|||
((__PRESCALER__) == WWDG_PRESCALER_2) || \ |
|||
((__PRESCALER__) == WWDG_PRESCALER_4) || \ |
|||
((__PRESCALER__) == WWDG_PRESCALER_8)) |
|||
|
|||
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) |
|||
|
|||
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) |
|||
|
|||
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ |
|||
((__MODE__) == WWDG_EWI_DISABLE)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Exported macros ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Enable the WWDG peripheral. |
|||
* @param __HANDLE__ WWDG handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) |
|||
|
|||
/**
|
|||
* @brief Enable the WWDG early wakeup interrupt. |
|||
* @param __HANDLE__ WWDG handle |
|||
* @param __INTERRUPT__ specifies the interrupt to enable. |
|||
* This parameter can be one of the following values: |
|||
* @arg WWDG_IT_EWI: Early wakeup interrupt |
|||
* @note Once enabled this interrupt cannot be disabled except by a system reset. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the selected WWDG interrupt has occurred or not. |
|||
* @param __HANDLE__ WWDG handle |
|||
* @param __INTERRUPT__ specifies the it to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT |
|||
* @retval The new state of WWDG_FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) |
|||
|
|||
/** @brief Clear the WWDG interrupt pending bits.
|
|||
* bits to clear the selected interrupt pending bits. |
|||
* @param __HANDLE__ WWDG handle |
|||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
|||
* This parameter can be one of the following values: |
|||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag |
|||
*/ |
|||
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified WWDG flag is set or not. |
|||
* @param __HANDLE__ WWDG handle |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag |
|||
* @retval The new state of WWDG_FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the WWDG's pending flags. |
|||
* @param __HANDLE__ WWDG handle |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be one of the following values: |
|||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
|||
|
|||
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
|
|||
* @param __HANDLE__ WWDG Handle. |
|||
* @param __INTERRUPT__ specifies the WWDG interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg WWDG_IT_EWI: Early Wakeup Interrupt |
|||
* @retval state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\ |
|||
& (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup WWDG_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup WWDG_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions **********************************/ |
|||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); |
|||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, |
|||
pWWDG_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup WWDG_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); |
|||
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); |
|||
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_HAL_WWDG_H */ |
|||
File diff suppressed because it is too large
@ -0,0 +1,201 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_ll_crc.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of CRC LL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_LL_CRC_H |
|||
#define STM32F4xx_LL_CRC_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx.h" |
|||
|
|||
/** @addtogroup STM32F4xx_LL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined(CRC) |
|||
|
|||
/** @defgroup CRC_LL CRC
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Write a value in CRC register |
|||
* @param __INSTANCE__ CRC Instance |
|||
* @param __REG__ Register to be written |
|||
* @param __VALUE__ Value to be written in the register |
|||
* @retval None |
|||
*/ |
|||
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) |
|||
|
|||
/**
|
|||
* @brief Read a value in CRC register |
|||
* @param __INSTANCE__ CRC Instance |
|||
* @param __REG__ Register to be read |
|||
* @retval Register value |
|||
*/ |
|||
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Reset the CRC calculation unit. |
|||
* @note If Programmable Initial CRC value feature |
|||
* is available, also set the Data Register to the value stored in the |
|||
* CRC_INIT register, otherwise, reset Data Register to its default value. |
|||
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit |
|||
* @param CRCx CRC Instance |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) |
|||
{ |
|||
SET_BIT(CRCx->CR, CRC_CR_RESET); |
|||
} |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Write given 32-bit data to the CRC calculator |
|||
* @rmtoll DR DR LL_CRC_FeedData32 |
|||
* @param CRCx CRC Instance |
|||
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) |
|||
{ |
|||
WRITE_REG(CRCx->DR, InData); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Return current CRC calculation result. 32 bits value is returned. |
|||
* @rmtoll DR DR LL_CRC_ReadData32 |
|||
* @param CRCx CRC Instance |
|||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits). |
|||
*/ |
|||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) |
|||
{ |
|||
return (uint32_t)(READ_REG(CRCx->DR)); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Return data stored in the Independent Data(IDR) register. |
|||
* @note This register can be used as a temporary storage location for one byte. |
|||
* @rmtoll IDR IDR LL_CRC_Read_IDR |
|||
* @param CRCx CRC Instance |
|||
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). |
|||
*/ |
|||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) |
|||
{ |
|||
return (uint32_t)(READ_REG(CRCx->IDR)); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Store data in the Independent Data(IDR) register. |
|||
* @note This register can be used as a temporary storage location for one byte. |
|||
* @rmtoll IDR IDR LL_CRC_Write_IDR |
|||
* @param CRCx CRC Instance |
|||
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) |
|||
{ |
|||
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; |
|||
} |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if defined(USE_FULL_LL_DRIVER) |
|||
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* USE_FULL_LL_DRIVER */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* defined(CRC) */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_LL_CRC_H */ |
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1,302 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_ll_iwdg.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of IWDG LL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32F4xx_LL_IWDG_H |
|||
#define STM32F4xx_LL_IWDG_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx.h" |
|||
|
|||
/** @addtogroup STM32F4xx_LL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined(IWDG) |
|||
|
|||
/** @defgroup IWDG_LL IWDG
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
|||
* @{ |
|||
*/ |
|||
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ |
|||
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ |
|||
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ |
|||
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
|
|||
* @brief Flags defines which can be used with LL_IWDG_ReadReg function |
|||
* @{ |
|||
*/ |
|||
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ |
|||
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
|
|||
* @{ |
|||
*/ |
|||
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ |
|||
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ |
|||
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ |
|||
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ |
|||
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ |
|||
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ |
|||
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Write a value in IWDG register |
|||
* @param __INSTANCE__ IWDG Instance |
|||
* @param __REG__ Register to be written |
|||
* @param __VALUE__ Value to be written in the register |
|||
* @retval None |
|||
*/ |
|||
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
|||
|
|||
/**
|
|||
* @brief Read a value in IWDG register |
|||
* @param __INSTANCE__ IWDG Instance |
|||
* @param __REG__ Register to be read |
|||
* @retval Register value |
|||
*/ |
|||
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
|
|||
* @{ |
|||
*/ |
|||
/** @defgroup IWDG_LL_EF_Configuration Configuration
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Start the Independent Watchdog |
|||
* @note Except if the hardware watchdog option is selected |
|||
* @rmtoll KR KEY LL_IWDG_Enable |
|||
* @param IWDGx IWDG Instance |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) |
|||
{ |
|||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Reloads IWDG counter with value defined in the reload register |
|||
* @rmtoll KR KEY LL_IWDG_ReloadCounter |
|||
* @param IWDGx IWDG Instance |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) |
|||
{ |
|||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
|||
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess |
|||
* @param IWDGx IWDG Instance |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) |
|||
{ |
|||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
|||
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess |
|||
* @param IWDGx IWDG Instance |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) |
|||
{ |
|||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Select the prescaler of the IWDG |
|||
* @rmtoll PR PR LL_IWDG_SetPrescaler |
|||
* @param IWDGx IWDG Instance |
|||
* @param Prescaler This parameter can be one of the following values: |
|||
* @arg @ref LL_IWDG_PRESCALER_4 |
|||
* @arg @ref LL_IWDG_PRESCALER_8 |
|||
* @arg @ref LL_IWDG_PRESCALER_16 |
|||
* @arg @ref LL_IWDG_PRESCALER_32 |
|||
* @arg @ref LL_IWDG_PRESCALER_64 |
|||
* @arg @ref LL_IWDG_PRESCALER_128 |
|||
* @arg @ref LL_IWDG_PRESCALER_256 |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) |
|||
{ |
|||
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Get the selected prescaler of the IWDG |
|||
* @rmtoll PR PR LL_IWDG_GetPrescaler |
|||
* @param IWDGx IWDG Instance |
|||
* @retval Returned value can be one of the following values: |
|||
* @arg @ref LL_IWDG_PRESCALER_4 |
|||
* @arg @ref LL_IWDG_PRESCALER_8 |
|||
* @arg @ref LL_IWDG_PRESCALER_16 |
|||
* @arg @ref LL_IWDG_PRESCALER_32 |
|||
* @arg @ref LL_IWDG_PRESCALER_64 |
|||
* @arg @ref LL_IWDG_PRESCALER_128 |
|||
* @arg @ref LL_IWDG_PRESCALER_256 |
|||
*/ |
|||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) |
|||
{ |
|||
return (READ_REG(IWDGx->PR)); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Specify the IWDG down-counter reload value |
|||
* @rmtoll RLR RL LL_IWDG_SetReloadCounter |
|||
* @param IWDGx IWDG Instance |
|||
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF |
|||
* @retval None |
|||
*/ |
|||
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) |
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{ |
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WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); |
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} |
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|
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/**
|
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* @brief Get the specified IWDG down-counter reload value |
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* @rmtoll RLR RL LL_IWDG_GetReloadCounter |
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* @param IWDGx IWDG Instance |
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* @retval Value between Min_Data=0 and Max_Data=0x0FFF |
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*/ |
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__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) |
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{ |
|||
return (READ_REG(IWDGx->RLR)); |
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} |
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|
|||
/**
|
|||
* @} |
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*/ |
|||
|
|||
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
|
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* @{ |
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*/ |
|||
|
|||
/**
|
|||
* @brief Check if flag Prescaler Value Update is set or not |
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* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU |
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* @param IWDGx IWDG Instance |
|||
* @retval State of bit (1 or 0). |
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*/ |
|||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) |
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{ |
|||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); |
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} |
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|
|||
/**
|
|||
* @brief Check if flag Reload Value Update is set or not |
|||
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU |
|||
* @param IWDGx IWDG Instance |
|||
* @retval State of bit (1 or 0). |
|||
*/ |
|||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) |
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{ |
|||
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); |
|||
} |
|||
|
|||
/**
|
|||
* @brief Check if flags Prescaler & Reload Value Update are reset or not |
|||
* @rmtoll SR PVU LL_IWDG_IsReady\n |
|||
* SR RVU LL_IWDG_IsReady |
|||
* @param IWDGx IWDG Instance |
|||
* @retval State of bits (1 or 0). |
|||
*/ |
|||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) |
|||
{ |
|||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); |
|||
} |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* IWDG */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32F4xx_LL_IWDG_H */ |
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Reference in new issue